Keypad Master:
;Abigail Stroh
;Lab 4
;Keypad Master Code
INCLUDE 'derivative.inc'
XDEF _Startup, main, _Viic, key_press ;temp_read
XREF __SEG_END_SSTACK
ORG $0060
FullKeypad: DS.B 1
IIC_addr: DS.B 1
msgLength: DS.B 1
current: DS.B 1
IIC_msg: DS.B 1
Column: DS.B 1
Row: DS.B 1
sendCheck: DS.B 1
Press: DS.B 1
Press2: DS.B 1
Temp: DS.B 1
Vtemp25: DS.B 1
Slope_high: DS.B 1
Slope_low: DS.B 1
Const: DS.B 1
Temporary: DS.B 1
ORG $E000
main:
_Startup:
LDHX #__SEG_END_SSTACK
TXS
CLI
LDA #$00
STA PTAPE
; Disable Watchdawg
LDA SOPT1
AND #%01111111
STA SOPT1
; set PTB0 pin as input for temp sensor
LDA #%11101111
STA APCTL1
; Set I2C pins
LDA SOPT2
ORA #%00000010
STA SOPT2
; Slave address
MOV #$10, IIC_addr
; Columns are inputs
LDA #$F0
AND PTADD
STA PTADD
; Rows are outputs
LDA #$3C
ORA PTBDD
STA PTBDD
; Rising edge sensitive
LDA #$0F
STA KBIES
BSET KBISC_KBIE, KBISC
LDA #$0F
STA KBIPE
LDA #1
STA sendCheck
;setting up A/D temp reading
;divide clock speed by 4
LDA #%00001010
STA TPMSC
;selecting PWM channel functions
LDA #$28
STA TPMC0SC
LDA #$4E
STA TPMMODH
LDA #$20
STA TPMMODL
;setting up A to D communication
LDA #%00000000
STA ADCCFG
LDA #%01011010
STA ADCSC1
;setting variable values
LDA #$36
STA Vtemp25
LDA #$B
STA Slope_low
LDA #$D
STA Slope_high
LDA #$19
STA Const
LDA #0
STA Temporary
JSR IIC_Startup_Master
*--------------------------------------------------------------
mainLoop:
LDA #%00010000
STA Row
BSET 2, PTBD
JSR Delay
BCLR 2, PTBD
LDA #%00100000
STA Row
BSET 3, PTBD
JSR Delay
BCLR 3, PTBD
LDA #%01000000
STA Row
BSET 4, PTBD
JSR Delay
BCLR 4, PTBD
LDA #%10000000
STA Row
BSET 5, PTBD
JSR Delay
BCLR 5, PTBD
LDA sendCheck
BNE EndLoop
LDA #1
STA sendCheck
LDA #1
STA msgLength
JSR IIC_DataWrite
EndLoop:
BRA mainLoop
*-----------------------------------------------------------------
*----Actual interrupt start----
_Viic:
;Clear interrupt
BSET IICS_IICIF, IICS
;Check if master
BRSET IICC_MST, IICC, _Viic_master ;Yes, should never need to be a slave
JSR Delay
JSR Delay
RTI
*----Check if transfer or recieve----
_Viic_master:
BRSET IICC_TX, IICC, _Viic_master_TX ;For transfer
BRA _Viic_master_RX ;For recieve
*----Transmit data----
_Viic_master_TX:
;Not last byte
LDA msgLength
SUB current
BNE _Viic_master_rxAck
;Is last byte
BCLR IICC_MST, IICC
BSET IICS_ARBL, IICS ;Arbitration lost, no code made for recovery
RTI
*----Check for acknowledge----
_Viic_master_rxAck:
;Ack from slave recieved
BRCLR IICS_RXAK, IICS, _Viic_master_EoAC
BRA _Viic_master_EoAC
;No ack from slave recieved
BCLR IICC_MST, IICC
RTI
*----End of address cycle, check for receive or write data---
_Viic_master_EoAC:
LDA IIC_addr
AND #%0000001
BNE _Viic_master_toRxMode
LDA IIC_msg
STA IICD
LDA current
INCA
STA current
RTI
*----Dummy read----
_Viic_master_toRxMode:
;Dummy read for EoAC
BCLR IICC_TX, IICC
LDA IICD
RTI
*----Recieve data----
_Viic_master_RX:
;Last byte to be read
LDA msgLength
SUB current
BEQ _Viic_master_rxStop
;2nd to last byte to be read
INCA
BEQ _Viic_master_txAck
BRA _Viic_master_readData
*----Stop condition----
_Viic_master_rxStop:
;Send stop bit
BCLR IICC_MST, IICC
BRA _Viic_master_readData
*----Acknowledge----
_Viic_master_txAck:
;Transfer acknowledge
BSET IICC_TXAK, IICC
BRA _Viic_master_readData
*----Read and store data----
_Viic_master_readData:
;Read byte from IICD and store into IIC_msg
CLRH
LDX current
;Store messafe into indexed location
LDA IICD
STA IIC_msg, X
;Increment current
LDA current
INCA
STA current
RTI
*----Initial configuration
IIC_Startup_Master:
;Set baud rate to 50kbps
LDA #%10000111
STA IICF
;Enable IIC and Interrupts
BSET IICC_IICEN,IICC
BSET IICC_IICIE,IICC
RTS
*----Initiate a transfer----
IIC_DataWrite:
;Initialize current
LDA #0
STA current
BSET 5, IICC ;Set master mode
BSET IICC_TX, IICC ;Set transmit
LDA IIC_addr ;Send slave address
STA IICD
RTS
Delay: ;General purpose delay
LDA #255
LOOP:
DECA
BNE LOOP
RTS
key_press:
BSET KBISC_KBACK, KBISC
LDA PTAD
STA Column
LDA Row
ADD Column
STA IIC_msg
;STA Press
;STA Press2
;CBEQA #$68,one_press
;CBEQA #$64,two_press
;CBEQA #$62,three_press
;CBEQA #$A8,four_press
;CBEQA #$A4,five_press
;CBEQA #$A2,six_press
;CBEQA #$48,seven_press
;CBEQA #$44,eight_press
;CBEQA #$42,nine_press
LDA #0
STA sendCheck
RTI
one_press:
LDA #1
STA Press
STA Press2
JMP mainLoop
two_press:
LDA #2
STA Press
STA Press2
JMP mainLoop
three_press:
LDA #3
STA Press
STA Press2
JMP mainLoop
four_press:
LDA #4
STA Press
STA Press2
JMP mainLoop
five_press:
LDA #5
STA Press
STA Press2
JMP mainLoop
six_press:
LDA #6
STA Press
STA Press2
JMP mainLoop
seven_press:
LDA #7
STA Press
STA Press2
JMP mainLoop
eight_press:
LDA #8
STA Press
STA Press2
JMP mainLoop
nine_press:
LDA #9
STA Press
STA Press2
JMP mainLoop
temp_read:
LDA Press
DECA
BEQ END
LDA Const
BLS slope_low
LDA ADCRH
LDA ADCRL
LDX Slope_high
DIV
STA Temp
SUB #3
STA Temp
LDA Const
SUB Temp
STA Temp
LDHX Temporary
ADD Temp
LDHX Temporary
END:
NOP
RTI
slope_low:
LDA ADCRL
LDX Slope_low
DIV
STA Temp
SUB #4
STA Temp
LDA Const
SUB Temp
STA Temp
LDHX Temporary
ADD Temp
STHX Temporary
RTI
LCD Slave:
; Working Lab 4 LCD Slave Louis Rosenblum
; Include derivative-specific definitions
INCLUDE 'derivative.inc'
; export symbols
XDEF _Startup, main, _Viic
; we export both '_Startup' and 'main' as symbols. Either can
; be referenced in the linker .prm file or from C/C++ later on
XREF __SEG_END_SSTACK ; symbol defined by the linker for the end of the stack
LCD_CTRL: EQU $00
LCD_DATA: EQU $02
E: EQU 0
RW: EQU 2
RS: EQU 1
ORG $0060
IIC_addr: DS.B 1
msgLength: DS.B 1
current: DS.B 1
IIC_MSG: DS.B 1
checkByte: DS.B 1
TIME: DS.B 1
CNTR0: DS.B 1
CNTR1: DS.B 1
CNTR2: DS.B 1
recieveCheck: DS.B 1
cluster: DS.B 1
bucket: DS.B 1
numba: DS.B 50
temp: DS.B 1
tens: DS.B 1
ones: DS.B 1
khuns: DS.B 1
ktens: DS.B 1
kones: DS.B 1
; code section
ORG $E000
MSG1: DC.B "1"
DC.B $00
MSG2: DC.B "2"
DC.B $00
MSG3: DC.B "3"
DC.B $00
MSG4: DC.B "4"
DC.B $00
MSG5: DC.B "5"
DC.B $00
MSG6: DC.B "6"
DC.B $00
MSG7: DC.B "7"
DC.B $00
MSG8: DC.B "8"
DC.B $00
MSG9: DC.B "9"
DC.B $00
MSG10: DC.B "0"
DC.B $00
MSG11: DC.B "A"
DC.B $00
MSG12: DC.B "B"
DC.B $00
MSG13: DC.B "C"
DC.B $00
MSG14: DC.B "D"
DC.B $00
MSG15: DC.B "E"
DC.B $00
MSG16: DC.B "F"
DC.B $00
CLEAR: DC.B "CLEAR"
MSGN: DC.B "n"
DC.B $00
MSGT: DC.B "t"
DC.B $00
MSGE: DC.B "e"
DC.B $00
MSGR: DC.B "r"
DC.B $00
MSGCOL: DC.B ":"
DC.B $00
MSGSPAC: DC.B " "
DC.B $00
MSGK: DC.B "K"
DC.B $00
MSGCOM: DC.B ","
DC.B $00
main:
_Startup:
LDHX #__SEG_END_SSTACK ; initialize the stack pointer
TXS
LDA #$FF
STA cluster
;Disable watchdog
LDA SOPT1
AND #%01111111
STA SOPT1
;IIC STUFF:
;PTA pins for SDA/SCL
LDA SOPT2
AND #%10000000
STA SOPT2
;set baud rate 50kbps
LDA #%10000111
STA IICF
;set slave address
LDA #$10
STA IICA
;enable IIC and interrupts
BSET IICC_IICEN, IICC
BSET IICC_IICIE, IICC
BCLR IICC_MST, IICC
LDA #$00
STA IIC_MSG
;and we back:
;set PTBD ports as outputs
BSET 0, PTBDD
BSET 1, PTBDD
BSET 2, PTBDD
BSET 3, PTBDD
BSET 4, PTBDD
BSET 5, PTBDD
BSET 6, PTBDD
BSET 7, PTBDD
;set PTAD ports as outputs
BSET 0, PTADD
BSET 1, PTADD
;interrupts enabled, use bus rate clock, 128 prescaler
LDA #%00101000
STA TPMC0SC
;7D00 = 32,000
LDA #$7D
STA TPMMODH
LDA #$00
STA TPMMODL
;Toggle overflow flag
LDA TPMSC
EOR #%10000000
STA TPMSC
*----Initialize checkByte----
LDA #0
STA checkByte
*----Initialize current----
LDA #0
STA current
*----Initialize LCD ports----
LDA #0
STA LCD_CTRL
STA LCD_DATA
;defining variable values
CLI ;enables interrupts
*----Initialize the LCD----
;delay
JSR FASTLOOP
;int command
LDA #$38 ;LCD int command
STA LCD_DATA
BSET E, LCD_CTRL ;clock in data
BCLR E,LCD_CTRL
;delay
JSR FASTLOOP
;int command
LDA #$38 ;LCD int command
STA LCD_DATA
BSET E, LCD_CTRL ;clock in data
BCLR E, LCD_CTRL
;delay
JSR FASTLOOP
;int command
LDA #$38
JSR LCD_WRITE
*----send function set command----
;8-bit but, 2 rows, 5X7 dots
LDA #$38
JSR LCD_WRITE
*----Send display contrl command
;display on , cursor off, no blinking
LDA #$0F
JSR LCD_WRITE
*----Send clear display command----
;clear display, cursor addr=0
LDA #$00
JSR LCD_WRITE
JSR FASTLOOP
*----Send entry mode command----
;increment, no display shift
LDA #$06
JSR LCD_WRITE
JSR IIC_Startup_slave
mainLoop:
LDA #$FF
STA cluster
JSR spit
BRA sit
part_dos:
BCLR 0,PTAD
BCLR 1,PTAD
LDA #$01
JSR LCD_WRITE
JSR FASTLOOP
BCLR 0,PTAD
BCLR 1,PTAD
LDA #$02
JSR LCD_WRITE
JSR FASTLOOP
LDA #$FF
STA cluster
BRA part_tres
sit:
NOP
NOP
LDA cluster
BEQ part_dos
BRA sit
sit2:
NOP
NOP
LDA cluster
BEQ part_tres
BRA sit2
part_tres:
LDA IIC_MSG
STA temp
LDHX #$000A
LDA temp
DIV
STA tens
STHX $0199
LDA $0199
STA ones
LDA tens
JSR compare
LDA ones
JSR compare
JSR C_press
JSR FASTLOOP
JSR spac_press
JSR FASTLOOP
LDA ones
ADD #$03
STA kones
LDA tens
ADD #$1B
STA ktens
LDHX #$000A
LDA ktens
DIV
STA khuns
STHX $0203
LDA $0203
STA ktens
LDA kones
CBEQA #$01,kapow
CBEQA #$02,kapow
CBEQA #$00,kapow
LDA khuns
JSR compare
LDA ktens
JSR compare
LDA kones
JSR compare
JSR k_press
BRA part_cuatro
part_cuatro:
NOP
NOP
LDA IIC_MSG
CBEQA #$38, get_ready
NOP
BRA part_cuatro
get_ready:
JMP mainLoop
RTS
compare:
CBEQA #$01,One
CBEQA #$02,Two
CBEQA #$03,Three
CBEQA #$04,Four
CBEQA #$05,Five
JSR compare2
JSR FASTLOOP
JSR FASTLOOP
RTS
kapow:
LDA ktens
ADD #$01
STA ktens
RTS
One:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
L3:
LDA MSG1,X
BEQ OUTMSG1
JSR LCD_WRITE
INCX
BRA L3
OUTMSG1:
LDA CLEAR
STA IIC_MSG
RTS
Two:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
L4:
LDA MSG2,X
BEQ OUTMSG2
JSR LCD_WRITE
INCX
BRA L4
OUTMSG2:
LDA CLEAR
STA IIC_MSG
RTS
Three:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
L5:
LDA MSG3,X
BEQ OUTMSG3
JSR LCD_WRITE
INCX
BRA L5
OUTMSG3:
LDA CLEAR
STA IIC_MSG
RTS
Four:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
L6:
LDA MSG4,X
BEQ OUTMSG4
JSR LCD_WRITE
INCX
BRA L6
OUTMSG4:
LDA CLEAR
STA IIC_MSG
RTS
Five:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
L7:
LDA MSG5,X
BEQ OUTMSG5
JSR LCD_WRITE
INCX
BRA L7
OUTMSG5:
LDA CLEAR
STA IIC_MSG
RTS
compare2:
CBEQA #$06,Six
CBEQA #$07,Seven
CBEQA #$08,Eight
CBEQA #$09,Nine
CBEQA #$00,Zero
RTS
Six:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
L8:
LDA MSG6,X
BEQ OUTMSG6
JSR LCD_WRITE
INCX
BRA L8
OUTMSG6:
LDA CLEAR
STA IIC_MSG
RTS
Seven:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
L9:
LDA MSG7,X
BEQ OUTMSG7
JSR LCD_WRITE
INCX
BRA L9
OUTMSG7:
LDA CLEAR
STA IIC_MSG
RTS
Eight:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
L10:
LDA MSG8,X
BEQ OUTMSG8
JSR LCD_WRITE
INCX
BRA L10
OUTMSG8:
LDA CLEAR
STA IIC_MSG
RTS
Nine:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
L11:
LDA MSG9,X
BEQ OUTMSG9
JSR LCD_WRITE
INCX
BRA L11
OUTMSG9:
LDA CLEAR
STA IIC_MSG
RTS
Zero:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
L12:
LDA MSG10,X
BEQ OUTMSG10
JSR LCD_WRITE
INCX
BRA L12
OUTMSG10:
LDA CLEAR
STA IIC_MSG
RTS
spit:
BCLR 0,PTAD
BCLR 1,PTAD
LDA #$01
JSR LCD_WRITE
JSR FASTLOOP
BCLR 0,PTAD
BCLR 1,PTAD
LDA #$02
JSR LCD_WRITE
JSR FASTLOOP
NOP
NOP
JSR E_press
JSR n_press
JSR t_press
JSR e_press
JSR r_press
JSR spac_press
JSR n_press
JSR col_press
JSR spac_press
NOP
RTS
splash:
BCLR 0,PTAD
BCLR 1,PTAD
LDA #$01
JSR LCD_WRITE
JSR FASTLOOP
BCLR 0,PTAD
BCLR 1,PTAD
LDA #$02
JSR LCD_WRITE
JSR FASTLOOP
RTS
C_press:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
L15:
LDA MSG13,X
BEQ OUTMSG13
JSR LCD_WRITE
INCX
BRA L15
OUTMSG13:
LDA CLEAR
STA IIC_MSG
RTS
E_press:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
L17:
LDA MSG15,X
BEQ OUTMSG15
JSR LCD_WRITE
INCX
BRA L17
OUTMSG15:
LDA CLEAR
STA IIC_MSG
RTS
n_press:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
N17:
LDA MSGN,X
BEQ OUTMSGN
JSR LCD_WRITE
INCX
BRA N17
OUTMSGN:
LDA CLEAR
STA IIC_MSG
RTS
t_press:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
T17:
LDA MSGT,X
BEQ OUTMSGT
JSR LCD_WRITE
INCX
BRA T17
OUTMSGT:
LDA CLEAR
STA IIC_MSG
RTS
e_press:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
E17:
LDA MSGE,X
BEQ OUTMSGE
JSR LCD_WRITE
INCX
BRA E17
OUTMSGE:
LDA CLEAR
STA IIC_MSG
RTS
r_press:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
R17:
LDA MSGR,X
BEQ OUTMSGR
JSR LCD_WRITE
INCX
BRA R17
OUTMSGR:
LDA CLEAR
STA IIC_MSG
RTS
col_press:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
COL17:
LDA MSGCOL,X
BEQ OUTMSGCOL
JSR LCD_WRITE
INCX
BRA COL17
OUTMSGCOL:
LDA CLEAR
STA IIC_MSG
RTS
spac_press:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
SPAC17:
LDA MSGSPAC,X
BEQ OUTMSGSPAC
JSR LCD_WRITE
INCX
BRA SPAC17
OUTMSGSPAC:
LDA CLEAR
STA IIC_MSG
RTS
k_press:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
K17:
LDA MSGK,X
BEQ OUTMSGK
JSR LCD_WRITE
INCX
BRA K17
OUTMSGK:
LDA CLEAR
STA IIC_MSG
RTS
com_press:
LDA #$00
JSR LCD_ADDR
CLRH
CLRX
COM17:
LDA MSGCOM,X
BEQ OUTMSGCOM
JSR LCD_WRITE
INCX
BRA COM17
OUTMSGCOM:
LDA CLEAR
STA IIC_MSG
RTS
IIC_Startup_slave:
;initialize slave settings
;set baud rate 50kbps
LDA #%10000111
STA IICF
;set slave address
LDA #$10
STA IICA
;enable IIC and interrupts
BSET IICC_IICEN, IICC
BSET IICC_IICIE, IICC
BCLR IICC_MST, IICC
RTS
_Viic:
;actual interrupt call
;DO I NEED TO SET UP THIS INTERRUPT IN PRM FILE???
;clear interrupt
BSET IICS_IICIF, IICS
;master mode?
LDA IICC
AND #%00100000
BEQ _Viic_slave ;yes
;no
;LDA PTBD
;AND #%00000000
;STA PTBD
RTI
_Viic_slave:
;check if arbitration is lost
;arbitration lost?
LDA IICS
AND #%00010000
BEQ _Viic_slave_iaas ;no
BCLR 4, IICS ;if yes, clear arbitration lost bit
BRA _Viic_slave_iaas2
_Viic_slave_iaas:
;check if IAAS = 1
;addressed as slave?
LDA IICS
AND #%01000000
BNE _Viic_slave_srw ;yes
BRA _Viic_slave_txRx ;no
_Viic_slave_iaas2:
;also checks if IAAS = 1
;addressed as slave?
LDA IICS
AND #%01000000
BNE _Viic_slave_srw ;yes
RTI ;if no exit
_Viic_slave_srw:
;check if read or write
;slave read/write
LDA IICS
AND #%00000100
BEQ _Viic_slave_setRx ;slave reads
BRA _Viic_slave_setTx ;slave writes
_Viic_slave_setTx:
;initialize transfer mode and send data
;transmits data
BSET 4, IICC ;transmit mode select
LDX current
LDA IIC_MSG, X ;selects current byte of message to send
STA IICD ;sends message
INCX
STX current ;increments current
RTI
_Viic_slave_setRx:
;initialize read mode and read IICD
;makes slave ready to receive data
BCLR 4, IICC ;receive mode select
LDA #0
STA current
LDA IICD ;dummy read
RTI
_Viic_slave_txRx:
;check if device is in transmit or receive mode
LDA IICC
AND #%00010000
BEQ _Viic_slave_read ;receive
BRA _Viic_slave_ack ;transmit
_Viic_slave_ack:
;check if master has acknowledged
LDA IICS
AND #%00000001
BEQ _Viic_slave_setTx ;yes, transmit next byte
BRA _Viic_slave_setRx ;no, switch to receive mode
_Viic_slave_read:
;actually read and store data
CLRH
LDX current
LDA IICD
STA IIC_MSG, X ;store received data in IIC_MSG
INCX
STX current ;increment current
LDA #$00
STA cluster
RTI
;and we back:
*----Routine sends LCD Data----
LCD_WRITE:
STA LCD_DATA
BSET E, LCD_CTRL
BCLR E, LCD_CTRL
JSR FASTLOOP
RTS
*----ROUTINE SENDS LCD ADDRESS----
LCD_ADDR:
BCLR RS,LCD_CTRL
STA LCD_DATA
BSET E,LCD_CTRL
BCLR E,LCD_CTRL
JSR FASTLOOP
BSET RS,LCD_CTRL
RTS
FASTLOOP:
LDA #6 ;load highest decimal value into accumulator for outer loop
;LDA #2
STA CNTR0
LOOP0:
LDA #100
STA CNTR1
LOOP1:
LDA #100 ;reset inner loop variable
STA CNTR2 ;load value into designated inner loop register
LOOP2:
LDA CNTR2
SUB #%00000001 ;subtracts 1 from inner loop
STA CNTR2 ;loads value into inner loops mem loc
BNE LOOP2 ;loop breaks once inner loop variable is set to 0
LDA CNTR1 ;loads the accumulator with value in outer loop memory
SUB #%00000001 ;subtract 1 from outer loop variable
STA CNTR1
BNE LOOP1 ; break loop once outer variable is 0
STA SRS
LDA CNTR0 ;loads the accumulator with value in outer loop memory
SUB #%00000001 ;subtract 1 from outer loop variable
STA CNTR0
BNE LOOP0 ; break loop once outer variable is 0
RTS
LED Slave:
; Working Lab 4 LED Slave Abigail Stroh
; Include derivative-specific definitions
INCLUDE 'derivative.inc'
; export symbols
XDEF _Startup, main, _Viic
; we export both '_Startup' and 'main' as symbols. Either can
; be referenced in the linker .prm file or from C/C++ later on
XREF __SEG_END_SSTACK ; symbol defined by the linker for the end of the stack
ORG $0120
IIC_addr: DS.B 1
msgLength: DS.B 1
current: DS.B 1
IIC_MSG: DS.B 1
; code section
ORG $E000
main:
_Startup:
LDHX #__SEG_END_SSTACK ; initialize the stack pointer
TXS
;Disable watchdog
LDA SOPT1
AND #%01111111
STA SOPT1
;IIC STUFF:
;PTA pins for SDA/SCL
LDA SOPT2
AND #%10000000
STA SOPT2
;set baud rate 50kbps
LDA #%10000111
STA IICF
;set slave address
LDA #$20
STA IICA
;enable IIC and interrupts
BSET IICC_IICEN, IICC
BSET IICC_IICIE, IICC
BCLR IICC_MST, IICC
LDA #$00
STA IIC_MSG
;and we back:
;set PTBD ports as outputs
BSET 0, PTBDD
BSET 1, PTBDD
BSET 2, PTBDD
BSET 3, PTBDD
BSET 4, PTBDD
BSET 5, PTBDD
BSET 6, PTBDD
BSET 7, PTBDD
;interrupts enabled, use bus rate clock, 128 prescaler
LDA #%00101000
STA TPMC0SC
;7D00 = 32,000
LDA #$7D
STA TPMMODH
LDA #$00
STA TPMMODL
;Toggle overflow flag
LDA TPMSC
EOR #%10000000
STA TPMSC
;defining variable values
;Feel like I don't need this
;slowing down LED speed
LDA #$FF
STA $0060
LDA #$C8
STA $0061
LDA #$06
STA $0062
;for Part B
LDA #$05
STA $0063
STA $0064
LDA #$03
STA $0065
;for Part C
LDA #$08
STA $0066
LDA #%00011000
STA $0067
LDA #$06
STA $0068
LDA #%00100100
STA $0069
LDA #%01000010
STA $0070
LDA #%10000001
STA $0071
CLI ;enables interrupts
JSR IIC_Startup_slave
mainLoop:
BRA mainLoop2
IIC_Startup_slave:
;initialize slave settings
;set baud rate 50kbps
LDA #%10000111
STA IICF
;set slave address
LDA #$10
STA IICA
;enable IIC and interrupts
BSET IICC_IICEN, IICC
BSET IICC_IICIE, IICC
BCLR IICC_MST, IICC
RTS
_Viic:
;actual interrupt call
;DO I NEED TO SET UP THIS INTERRUPT IN PRM FILE???
;clear interrupt
BSET IICS_IICIF, IICS
;master mode?
LDA IICC
AND #%00100000
BEQ _Viic_slave ;yes
;no
;LDA PTBD
;AND #%00000000
;STA PTBD
RTI
_Viic_slave:
;check if arbitration is lost
;arbitration lost?
LDA IICS
AND #%00010000
BEQ _Viic_slave_iaas ;no
BCLR 4, IICS ;if yes, clear arbitration lost bit
BRA _Viic_slave_iaas2
_Viic_slave_iaas:
;check if IAAS = 1
;addressed as slave?
LDA IICS
AND #%01000000
BNE _Viic_slave_srw ;yes
BRA _Viic_slave_txRx ;no
_Viic_slave_iaas2:
;also checks if IAAS = 1
;addressed as slave?
LDA IICS
AND #%01000000
BNE _Viic_slave_srw ;yes
RTI ;if no exit
_Viic_slave_srw:
;check if read or write
;slave read/write
LDA IICS
AND #%00000100
BEQ _Viic_slave_setRx ;slave reads
BRA _Viic_slave_setTx ;slave writes
_Viic_slave_setTx:
;initialize transfer mode and send data
;transmits data
BSET 4, IICC ;transmit mode select
LDX current
LDA IIC_MSG, X ;selects current byte of message to send
STA IICD ;sends message
INCX
STX current ;increments current
RTI
_Viic_slave_setRx:
;initialize read mode and read IICD
;makes slave ready to receive data
BCLR 4, IICC ;receive mode select
LDA #0
STA current
LDA IICD ;dummy read
RTI
_Viic_slave_txRx:
;check if device is in transmit or receive mode
LDA IICC
AND #%00010000
BEQ _Viic_slave_read ;receive
BRA _Viic_slave_ack ;transmit
_Viic_slave_ack:
;check if master has acknowledged
LDA IICS
AND #%00000001
BEQ _Viic_slave_setTx ;yes, transmit next byte
BRA _Viic_slave_setRx ;no, switch to receive mode
_Viic_slave_read:
;actually read and store data
CLRH
LDX current
LDA IICD
STA IIC_MSG, X ;store received data in IIC_MSG
INCX
STX current ;increment current
RTI
;and we back:
mainLoop2:
;added because Part_D was out of range of mainLoop
;JSR _Viic
LDA IIC_MSG
;JMP E_press for testing each input
CBEQA #$68,One
CBEQA #$64,Two
CBEQA #$62,Three
CBEQA #$61,A_press
CBEQA #$A8,Four
CBEQA #$A4,Five
CBEQA #$A2,Six
CBEQA #$A1,B_press
CBEQA #$48,Seven
CBEQA #$44,Eight
CBEQA #$42,Nine
CBEQA #$41,C_press
CBEQA #$38,E_press
CBEQA #$34,Zero
CBEQA #$32,F_press
CBEQA #$31,mainLoop3
BRA mainLoop2
One:
LDA #%00001000
STA PTBD
BRA mainLoop2
Two:
LDA #%00000100
STA PTBD
BRA mainLoop2
Three:
LDA #%00001100
STA PTBD
BRA mainLoop2
A_press:
LDA #%00000101
STA PTBD
BRA mainLoop2
Four:
LDA #%00000010
STA PTBD
BRA mainLoop2
Five:
LDA #%00001010
STA PTBD
BRA mainLoop2
Six:
LDA #%00000110
STA PTBD
BRA mainLoop2
B_press:
LDA #%00001101
STA PTBD
BRA mainLoop2
Seven:
LDA #%00001110
STA PTBD
BRA mainLoop2
Eight:
LDA #%00000001
STA PTBD
JMP mainLoop2
Nine:
LDA #%00001001
STA PTBD
JMP mainLoop2
C_press:
LDA #%00000011
STA PTBD
JMP mainLoop2
mainLoop3:
BRA D_press
E_press:
LDA #%00000111
STA PTBD
JMP mainLoop2
Zero:
LDA #%00000000
STA PTBD
JMP mainLoop2
F_press:
LDA #%00001111
STA PTBD
JMP mainLoop2
D_press:
LDA #%00001011
STA PTBD
JMP mainLoop2
Parameters File:
/* This is a linker parameter file for the mc9s08qg8 */
NAMES END /* CodeWarrior will pass all the needed files to the linker by command line. But here you may add your own files too. */
SEGMENTS /* Here all RAM/ROM areas of the device are listed. Used in PLACEMENT below. */
Z_RAM = READ_WRITE 0x0060 TO 0x00FF;
RAM = READ_WRITE 0x0100 TO 0x025F;
ROM = READ_ONLY 0xE000 TO 0xFFAD;
ROM1 = READ_ONLY 0xFFC0 TO 0xFFCF;
/* INTVECTS = READ_ONLY 0xFFD0 TO 0xFFFF; Reserved for Interrupt Vectors */
END
PLACEMENT /* Here all predefined and user segments are placed into the SEGMENTS defined above. */
DEFAULT_RAM, /* non-zero page variables */
INTO RAM;
_PRESTART, /* startup code */
STARTUP, /* startup data structures */
ROM_VAR, /* constant variables */
STRINGS, /* string literals */
VIRTUAL_TABLE_SEGMENT, /* C++ virtual table segment */
DEFAULT_ROM,
COPY /* copy down information: how to initialize variables */
INTO ROM; /* ,ROM1: To use "ROM1" as well, pass the option -OnB=b to the compiler */
_DATA_ZEROPAGE, /* zero page variables */
MY_ZEROPAGE INTO Z_RAM;
END
STACKSIZE 0x40
VECTOR 0 _Startup /* Reset vector: this is the default entry point for an application. */
VECTOR 18 key_press
VECTOR 17 _Viic
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