Project 0: Vivado and Basys3 Tutorial

B441/E315, Fall 2018

Due Date: None

Description

This tutorial shows the steps in a digital design project using Xilinx Vivado design suite and Digilent Basys 3 FPGA board. You will learn how to use Vivado tool to create a digital design and implement the design on an FPGA circuit located on the Basys3 board.

Here you will design and implement a circuit which consists of a slide switch and a light emitting diode (LED). If the slide switch is up, the LED will light up (will be turned on). If the slide switch is down, the LED will turn off.

This is a starter project with very little hands-on work, but it is a good reference if you ever forget how to start and complete a lab project.

Create a project

 Default Part

Create Design Source File

Now we will add our first Verilog source file

 

module top(

        input sw,

        output led

        );

assign led = sw;

endmodule

 

Create Constraints File

Now we will add our first constraints source file.  This tells Vivado how the inputs and outputs of the top-level verilog file map to the real inputs and outputs of the Basys3 board.  

set_property PACKAGE_PIN V17 [get_ports {sw}]

set_property IOSTANDARD LVCMOS33 [get_ports {sw}]

set_property PACKAGE_PIN U16 [get_ports {led}]

set_property IOSTANDARD LVCMOS33 [get_ports {led}]

Create Simulation File (AKA testbench)

We are now going to run a simulation to ensure that our verilog code is correct.

`timescale 1ns / 1ps //specify how detailed of a simulation we want to run

module testbench();

        wire led; //wires are for module outputs

        reg sw; //reg(isters) are for module inputs

 

        //connect our module for testing

        top top0 (

            .led(led),

            .sw(sw)

        );

 

        initial

        begin

 

            #100 // a 100 nanosecond delay

 

            //set sw to "low" and test that the led also goes "low"

            sw = 0;  // set sw=0

            #100 //another 100 nanosecond (ns) delay

            // if the led is not "low" fail with an error message

            assert( led == 0) else $fatal(1, "LED==0 Failed");

 

            #100 //100 ns delay

            sw = 1; //now we try setting the switch to “high”

            #100

            //if the LED is not “high”, fail with an error message

            assert( led == 1) else $fatal(1, "LED==1 Failed");

 

            #100 // another 100ns delay, just for funzies

          //hooray, we passed the test bench!

            $display("@@@Passed");

            $finish;

 

        end

 

endmodule

Checkpoint

Now we should have all of our source files.  Your setup should look like the following:

Running a Simulation

Now we are going to run our simulation, and observe the outcomes of our testing.

sw = 0;  // set sw=0

in our simulation file. We told the simulation to set sw to 0, so now it knows its value.  Once the simulation knew the value for sw, it could calculate the value for led, because we told it

 assign led = sw;

in our source file.

Hardware Synthesis

Programming the FPGA

This process will (finally) program the FPGA.  

 

Testing your FPGA

 You should now be able to test your FPGA.  When you flip the right-most switch, the corresponding LED should also toggle.  

This concludes the Vivado tutorial lab.