In this lab, you will are expected to design fabricate and test at least four medium-sized analog/mixed-signal projects under the guidance of a mentor (TA, professor). You have been well prepared in practical analog design, and in this lab, you will use all your skills to implement real-world designs on time successfully and well documented. Rather than follow a list of instructions to complete a laboratory, you will be given specification to solve projects, and then we will help you implement a solution by making sure we provide the expertise, equipment, and supplies to get the job done. If you need a review or there is a new topic that you do not understand fully yet, you have to identify this and come up with an education plan to get you the knowledge you need. While it is fine to ask the TA or professor about topics, you will be expected to try at least to find the information yourself before posing your questions. (This is just like work!)

Design Flow of Projects

Although each project will be different, there are general steps that you should documents and follow for every design. Your grade will not only depend on whether the circuit performed properly or not, but also on how you followed the process. Of course following the process will lead to a successful working project.

Define the problem and fully understand the specifications.
Research previous attempts to solve the problem, or similar problems.
Come up with a behavioral model of a system that solves the problem.

Check to see if boundary conditions such as slew rate, power supply rails, VOS will be an issue.
Start to think of how this circuit will be tested.

Implement the circuit in LTspice with realistic parts. Make sure the results match the behavioral model in the range of voltages and currents specified.

Determine what resistor, capacitor, inductor tolerances your circuit can withstand and still meet specification
Design practical test vectors to prove that your circuit works.

Create a prototype implementation plan. This is a scale drawing of how the parts will be placed and connected with wires.
Prototype the circuit and measure results.
Compare with ideal performance.
Document results.
Implement with a PCB (possibly)

Each week in the lab will cover specific steps. For instance, during week 1 of a project, you would be responsible for completing steps 1-3. Week 2 you would be responsible for Step 4. During the final week, you would be responsible for steps 4-8. Some projects will involve PCB manufacture.

There are some things that need to be presented formally.

Engineers need to be able to automate any repetitive task that they do to improve their productivity. This automation is usually done with a scripting language. You will learn python and the associated packages that support the automation of electronic testing. The other topic that needs to be learned formally is analog to digital and digital to analog conversion. These labs will consist of the first few weeks of the lab. Once these skills are learned then, you will be ready for the design projects.

There are some tools that every EE student has to know how to use correctly to be a successful analog/system engineer.

Spice: There are many versions of spice, but the one that will be supported in the lab is LTspice from linear technology. LTspice is a fully functional spice program that is even used by Linear’s competitors. As of this time Linear was purchased by Analog Devices. To get the latest version of the tool, do an internet search for LTspice.

Multi-meters (Fluke 45)

Power Supply (Agilent E3631A)

Oscilloscope (Agilent 54621A)

PC Board Layout (Diptrace): To create a system that can be reliably used, or sold, it has to be implemented on a PCB. Diptrace has a free "lite" version capable of 500pins and two layers. The software can be downloaded, and tutorials can be from:

http://www.diptrace.com/

PCB in box:

http://www.pcbfx.com/

Protoboard Layout, board layout, Arduino Interface:

http://fritzing.org/

Week 1: Spice modeling of OPAMP parameters VOS and RIN, and a voltage controlled current source

Introduction

The goal of 124L is to turn you into an "Analog Guru". To do this, you need to learn about how OPAMPS work, not necessarily to design OPAMPS (EE223), but to use them at a high level. As practicing engineers, you will be pushing the envelope of what is possible, and so you need to know how an OPAMP works on the inside to master low power, and/or high-frequency design methodologies.

In general, the OPAMP labs so far have been designed to work in regions where OAMPS act ideal, so we can get you started on designing things. You should already know about GBW limitations on filters, and VOS effects on integrators. You might have already had to deal with non-ideal effects because the Quadratic Integrate and Fire neuron was chosen in part because it is sensitive to VOS variations. Some LM741 parts statistically had a small VOS, and the circuit would work, some did not, and the circuit would not work. Choosing a part with a low VOS made sure the circuit did work.

Given that you have had many analog courses, you will be asked to do more on your own and read applications notes.

Lab Exercises:

VOS: Offset input voltage

Figure 1: Circuit used to measure VOS. (OPAMP is level 2.)

The circuit shown in Figure 1 is a test circuit designed to measure the offset voltage (VOS on a data sheet) of an OPAMP. Mismatches cause the offset voltage in the transistors used in the differential input stage. (This will be covered later.) Some spice models include it and others do not. You can use the above circuit to determine if there is an offset voltage and what the value is.

Derive what the output voltage will be of Figure 2 if VOS is not-zero. Assume an ideal OPAMP, except that VOS is non-zero.
Simulate the VOS test circuit for the universal OPAMP with a VOS of 60 (You can edit the parameter in the universal OAMP or use the method shown in Figure 2.) and the LT1006.

What did you measure in each case? Did it match predictions?

Repeat the simulation for the universal OPAMP only, but vary the R1 resistance to be according to the following table:

R1 (	R2 (	Vout_universal
50k	50k
50.5k	50k
49.5k	50k
52.5k	50k
47.5k	50k
55k	50k
45k	50k

Describe how the resistor variance affects the measure of VOS.
Choose and justify a resistor tolerance maximum to be able to measure VOS accurately.

Figure 2: Modeling VOS with a DC voltage source.

Modeling RIN

The definition of that is commonly used is the input resistance to the OPAMP seen when one input pin is set to ground. If we look at Figure 3, and if we assume U1 is ideal, short VIN- to ground then the input impedance is (See Figure 4. ) Our experiment will not find or , but we will estimate . (See Figure 5.)

Figure 3: How to model the effects of RIN and RDIFF. The universal OPAMP model has 500MΩ RIN.

Figure 4: "Graphical Derivation" of RIN. A: Original circuit, B: Ideal OAMP removed, C: Final circuit.

Extracting “RIN”:

Figure 5: Circuit used to estimate RIN. (OPAMP is level 2.)

Derive an equation for Vout from Figure 5 if the OPAMP is ideal except for a is not equal to zero. Here is a video hint.
Find the R1 value that causes the output voltage to drop by ½, this will be our value of RIN.

A Circuit that is sensitive to VOS

Figure 6: Measuring the Effect of VOS.

Derive the output relationship of the circuit shown in Figure 6.
How long will it take for the circuit’s output voltage to go from zero volts to the power supply if the offset voltage is the value shown in the figure?
Using any modeling technique you like, simulate and find out how long it will take to reach the power supply voltage.

A circuit that is sensitive to RIN:

Figure 7: Showing how RIN can change the DC gain of a low pass filter.

Derive the transfer function of the above circuit if the OPAMP is ideal except RIN infinite.
Simulate the circuit shown in Figure 7.
What is the maximum value of R1 can be and the DC gain will be within 1% of 0dB.

Figure 8: Showing how RIN can change the cut-off frequency of a high pass filter.

Derive the transfer function of the above circuit if the OPAMP is ideal except RIN infinite.
Simulate the circuit shown in Figure 8.
What is the maximum value of C1 can be and the cut off frequency will be within 1% of the ideal cutoff frequency?

Howland Current Pump:

Figure 9: Howland current pump.

Derive the relationship between the input voltage and the current through RL for Figure 9. How to formally document a derivation and a hint on how to do it for this particular circuit can be found here.

Notes on why this circuit works even with positive feedback can be found here. (It also shows how the circuit might not work and how to counteract this.)

Choose two sets of values for R1=R2=R3=R4 such that when the input voltage is between , the output current is and .
Simulate your circuit and comments on any differences.

Summary of experiments:

Circuit	Reference	Notes/Tips	Simulation Conditions	Directions
VOS Test	LT1006 Data Sheet Page 10	We do not have special resistors. Measure R values to make sure they match. Make power supplies. Here is a video. There are no notes to go with it.	Pick any OMAMP from Linear and the universal OPAMP Use an .op (DC simulation) Do one where the 50k are equal when they at 1%, 5% and 10% different.	Do this for the LT1006 and the universal OPAMP. Set the universal OPAMP to have a VOS of 60. If you are stuck, here a circuit you can start with.
RIN estimation	Page 1.41 Page 2	Unfortunately, the definition can vary. This unclear definition is ok because what we need to do is not find Rin exactly, but find what values of resistors we can use and have RIN not be affecting the circuit. Use the circuit.	Pick any OMAMP from Linear and the universal OPAMP Use an .op simulation and vary R1 from 1 to 10 logarithmically with 5 steps per decade.	Do this for the LT1006 and the universal OPAMP. Set the universal OPAMP to have a RIN of 1. If you are stuck, here a circuit you can start with. IN is where Vout drops to ½ of Vin.
Inverting Integrator Circuit	Here are some notes. Here is the EE122 lab manual	The offset voltage will act as an input, and over time the output will go to the positive or negative rail	Set RC=1 and keep the same power supplies. Set the input to zero voltage and do a transient simulation for 5000 seconds.	Do this for the universal OPAMP. Set the universal OPAMP to have a VOS of 60, and 600 If you are stuck, here a circuit you can start with.
Unity Gain buffer with RC low pass Filter as an input, and high pass filter.		Choose an Fc that is at least 100 times smaller than the GBW of the OPAMP. Keep R values above 1k to present excessive current draw.	Do an AC simulation form 1 to 10MHz (or 10 times the GBW), with at least 20 points per decade.	Here is a circuit to get started with.
Voltage controlled current Source (Howland Current Pump)	App note from TI.	Make sure that	Use the universal OPAMP with VOS=0V, RIN=500M and AVOL greater than 1M.	Here is a circuit to start with.

Post-Lab

Finish all simulations and watch all videos, and by hand do all derivations, and by answer all questions.

Lab report:

Formally present all that you were supposed to do in the lab this past week. The introduction can be why these circuits are essential, and all the derivations can be in the theory section. The methodology will have the details of your simulations, and the results and discuss section will have all plots and simulated data. Comparisons will be made between theory and simulation, and reasonable explanations of any differences will be provided. Use the standard lab report format.

Common lab report complaints/questions:

Why do I have to write a lab report? I know what I learned. Documenting your designs so that others can rapidly read about what you have completed is an essential skill that engineers need. Alumni that I talk to tell me that they appreciate the professors that were picky about lab reports. You will be a leader one day, and leaders need to be able to communicate. Writing the lab report helps you learn the material better. As you try to explain differences between simple theory, simulation results, and measured data, you will learn the material. It is like when you explain how to do an HW to a friend. Your friend learns, but you learn more, as you try and figure out the best way to explain the solution.
Why are you so picky about the figures? I did not know the format. Professionals in the industry look at the figures first. If your figures are not to the company standard, or hard to read they will feel you do not know how to follow instructions. (BTW the format has been the same since EE110L, and there are extensive videos, templates, and documents that show the proper way to create figures.)
It took me a long time to write the lab report. If you think that you are spending too much time on your reports, most likely you are right. The solutions are not to lower the standard but to learn how to do things quickly. In this class some tips are:

The biggest time saver is to know the theory so that in the lab you know right away if your experiment is working or not. Trying to explain bad data takes a lot of time.
Set up your LTspice environment correctly and use the Tools… Copy bitmap function.

Figure 10: Tools.. Copy.. Bitmap.

Use the keyboard short cuts for equation editor.
Do one figure in the lab, and have your TA scan it for issues.
Do not write every algebraic step in a derivation. Here is a video example.

Set up the relevant equations and link it to a figure.
Explain any approximations or transformations.
Show the final equation.

A zero for wrong figures or missing components in a lab report is too harsh. If an employer reads a document that is missing something or not to standard, you might be fired. That is harsh. We at least let you re-write it with no penalty.

Week 2: Physical Verification of OPAMP parameters VOS and RIN, and a voltage controlled current source

Introduction

While spice simulation is an excellent tool to explore the design space of circuit design, it does not model the real world "perfectly". (That is why it is called a model.) Spice has some limitations that require the fabrication and test of a circuit to show what will happen:

Spice assumes the values of R, L, C, voltage or current sources are a "lumped parameter". Assuming that elements are a lumped parameter means that spice does not simulate a circuit's performance with Maxwell's equations, but simplified equations such as .
It does not simulate the R, L, and C of wires. (You can add these in by hand.)
It does not simulate the statistical variations of parameters of R, LC, X, Avol, etc. (Note you can attempt this with a Monte Carlo Analysis, but these simulations take a long time.)
You can simulate the effects of noise, but it does not automatically simulate the effect of a 60Hz noise source, or the fact all wires are antennas.
It does not simulate the fact that the parameters change when the device heats up over time. (You can change the temperature of a simulation, but the temp stays fixed.)

Given these limitations, some analog gurus like the Late Bob Pease would tell you SPICE is worthless. Spice is still accurate enough to explore design and narrow down the possibilities of what will work.

In this week's lab, you will build and test the circuits from week 1. We will use the LT1037 or LM833 OPAMP, but any OPAMP you have can be used, make sure that your LTspice simulations match what you built.

Build the circuit shown in Figure 11 using the resistor values shown. Be sure to measure the resistor values before you fabricate the circuit so that you can analyze differences in theoretical vs. measurements

While you may use a proto-board, they are devils designed to waste your time. (A better way would be to use a solder board.) Make sure to copy down the test equipment, and their tolerances. Take pictures of the circuit as well. If you can get a picture of the circuit with the measurement being shown even better. Try to measure three different OPAMPS of the same type.

Hint: Read the datasheet for the OPAMP in question. Make sure the power supplies can handle.

Some OPAMPS do not have LTspice Models. Use the datasheet and the universal OPAMP model to model OPAMPS, not in the tool. How to do this is shown in the EE122 manual.

Figure 11: Circuit used to measure VOS.

RIN circuit

Build the circuit shown in Figure 12 using the biggest range variable resistor you can find.

Vary the potentiometer until Vout is ½ of Vin. Measure the value of the potentiometer, and this will be an estimate of RIN. This experiment might not work given that RIN can be . If this does not work, see if you can get Vout to drop to 90%, or even 95% and back calculate what RIN should be. If you can max the potentiometer and nothing happens, you can try adding a 1 or 10M resistor in series with the potentiometer. Many datasheets do not show RIN. You might not find RIN exactly, but you can state that RIN is greater than a value.

Figure 12: Circuit used to estimate RIN.

Howland Current Pump circuit

Build the circuit shown in Figure 13. Keep the value of RL the same, but fix R1=R2=R3=R4 to be 1. Be sure to measure these values before you build the circuit, for analysis later.

Step Vin from -1 to 1V in steps of .1V and measure the current through RL. Do this two ways:

Use an ammeter though RL,
Measure the values of RL and Vout and calculate . The 2 is not a typo.

Some students find that calculating the current does not work. VOS of 1m or 10mV can cause issues, with this method. For instance, a 1mV offset, and can cause the output voltage to be in the positive mV range and look like it is not changing at all. LM741’s have a high output voltage.

Figure 13: Howland Current Pump

Based on your equipment’s data sheet (Hint R’s have to be less than RIN.), calculate what the smallest current you can measure with the set up shown in the above figure. You can change Vin to a value that the voltage supply is capable of. Measure that smallest current.

Lab report:

Formally present all that you were supposed to do in the lab this past week. The introduction can be why these circuits are essential, and all the derivations can be in the theory section. The methodology will have the details of your simulations and measurements (you can grab the relevant portions in the previous lab report), and the results and discussion section will have all plots, simulated data, and measured data. Discuss differences between theory, simulated results and measured results. If you proposed a reason for the variance between simulation and measured results, you must back it up. For instance, if you claim the reason the values do not match is the fact the resistor values used in the simulation were not precisely the same ones used in the real circuit, back this up by simulating the actual resistor values you used. Some standard reasons for an experiment not to give for the exact measured values not matching simulation:

R, L, and C values are not precisely the same.
AVOL, GBW, VOS, RIN all vary statistically. OPAMP data sheets, in general, show the worst case in the case the smallest AVOL, RIN and GBW, and the largest VOS.
Protoboards are a real source of trouble. Parts can wiggle and cause significant noise.
The 60Hz hum from the environment.
Wiring resistance, capacitance, and inductance are not simulated.
Some voltages occur when two different metals are connected.
Use standard lab report format.

Week 3/4: Introduction test automation with Python

Introduction

Lab 1 serves as an introduction to python (http://www.python.org/, great for tutorials, but does not install this version) programming and automation of analog testing of circuits.

If you wish to install python on your PC-based laptop or you need to learn python read chapter 3 of this tutorial. Make sure it is version 2.7, not 3.X.

This software is freely distributable and can be loaded on your laptop which you can bring into lab. This software is installed on the laboratory computers as well.

If you are installing this on your laptop, you have to install the GPIB drivers.

If you are using an EE lab computer, you do not have to install the GPIB drivers, but you have to install pyvisa from the Enthought environment, canopy. You have to install pyvisa if you are using your laptop as well.

Pyvisa is a “wrapper” for GPIB, USB devices. All the docs are located here.

To install pyvisa (You must do this once):

Start canopy by clicking on the Canopy icon
Click on the package manager as shown in Figure 14.

Figure 14: Starting Package manager.

Search for pyvisa in available, click on it and then click install as shown in Figure 15.

Figure 15: Installing pyvisa

If it was correctly installed, then you should see Figure 16.

Figure 16: Pyvisa properly installed.

Checking to see if your installation is correct

The first thing to do is to identify the GPIB address of each piece of equipment. Here is a video on how to do this for an oscilloscope (Agilent, or Keysight). Here is a video on how to do this for a Keysight function generator.
Download this file and open up in Canopy.
Click on the link, and you should get a screen that looks like Figure 17.

Figure 17: Download file from Dropbox.

Left click on the Download button in the upper right corner of your browser as in Figure 18, and then select Direct download.
Open file

Figure 18: Click on Direct download.

Turn on the function generator and scope and make sure they are connected with a GPIB cable to the computer with a USB/GPIB adapted.
Edit the GPIB address to that of the function generator that you found in step one. (Should be 10)
Run the file. You should get back the information about the function generator.

If you get a pack “visa not found”. You need to install pyvisa
If the command “print 100” is giving a syntax error, you are using python 3.0. you need to use python 2.7

To reset your environment got to Tools... Troubleshoot… Reset Python environment (Figure 19).

Figure 19: Resetting Python Environment

Lab Exercise

You need to follow the pyvisa tutorial outlined here. Use the function generator or oscilloscope as the measurement device instead of what tutorial has.

Figure 20: The user guide is the tutorial.

Datasheet Keysight 33500B function generator.

Manual Keysight 33500B function generator.

Manual Agilent oscilloscope

Programmer guide Agilent oscilloscope

Manual Keysight oscilloscope

Programmer guide Keysight oscilloscope

FFT oscilloscope applications note.

When you start python in the lab for the first time it might ask you to create a new environment, select yes, create new environment.

Sample python files that should work in Lab:

Program used to make multiple objects for GPIB devices and to check the addresses.
Program that uses the oscilloscope.
Program that uses the function generator and oscilloscope.
Program to sweep voltage and measure current. Uses power supply which does not look like it is hooked up to GPIB in Lab. Ask for GPIB cable.

Post-Lab

Your task is to create an automated Bode plot test system using python, the function generator and oscilloscope with the circuit shown in Figure 21.

Verify the calibration of the probes of your probes first!

Use the oscilloscope.
Use the oscilloscope and function generator.
Verify with an RC low pass filter.

Please watch these videos. It will save you time and heartache.

The Bode plot needs to have magnitude and phase data. Verify the circuit at node X and Out for both time cut off frequencies. You can see what should have by running this file in LTspice. Given that you are effectively building a test system, you need to verify the function generator and oscilloscope you need to verify the system first. Create an RC low pass filter by twisting an R and C together at the midpoint. (The RC value should give a cutoff frequency around 10KHz.) Measure the R and C and predict where the -3dB point and phase frequency and make sure your function generator probes, and oscilloscope give you this value. Verify the low-frequency gain and phase too. (~10Hz). Read about the perils of not calibrating your instruments here. Note the higher cutoff frequency will have some GBW non-ideal BODE plot. You can make a BODE pot two ways:

One is a classic method where you measure the ratio of Vout/Vin and delay between Vout and Vin while sweeping a sin wave input to have at least 5 points per decade.
The second method is to use an FFT, with an impulse response or step response.

FFT oscilloscope applications note.
EE110L lab manual
Video using LTspice.

Figure 21: Circuit used to verify the Bode Plot Generator.

Lab report:

For this assignment turn in individual reports in electronic form to canvas showing that you have verified the functionality of your OPAMP test circuit, and your python code.

The report should show how you verified the functionality of your system.

Use the standard report format.
Theory shows the derivation of all circuits that you used for this lab report.
Introduction would explain the uses of the Bode Plot. Explain why this measurement should be automated.
Show the Bode plot of an RC circuit of your choosing. ( is around 10kHz) that you did by “hand”. (You can use the measurement functions, ratio, and phase from the oscilloscope.) (By “hand” means non-automated.)

Compare this to a Bode plot from LTspice for the RC lowpass filter you just made.
Explain differences (R and C tolerances? The measurement accuracy of scope, Calibration or probes and scope, are things to investigate. Does the R have a parasitic capacitance, inductance? Does the capacitor have parasitic R and L)

Create the automated Bode plot program and then test it with the circuit you used above.

Compare this to the other measurements and explain differences.

Create a Bode plot for the circuit shown in Figure 21.

By this time if there are any differences, you either fixed them or explained them.
The circuit in Figure 21 might be unstable (Yes, EE110 is back.) If the output of the RC lowpass filter is correct and there are oscillations on the output of the OPAMP, then the OPAMP is unstable. Here are some tips on fixing this, but sometimes just adding an output resistor to ground (~) works.

You can end up measuring a lot of wrong signals and not realize until you are writing up your report. Really, really understand the theory of passive low pass filters. Gain and phase should be 0 well below the cutoff frequency, the -3dB point should occur at . (This can vary by if the probes have not been matched or calibrated.

Week 5: MOS cascode and current mirrors.

Introduction:

We have seen that single transistor circuit can be used to create amplifiers and we have used resistors to bias these transistor circuits in subthreshold, moderate inversion and full inversion. While resistors can be made to very tight tolerances, they still take up a large amount of board space. (Yes the 601 surface mount parts use in EE122 were tiny, they are still large compared to the parts on the inside of an integrated circuit.) While it is true that resistors can be fabricated on the same die as a transistor, they use a large amount of surface area. It has been found that it is better when designing analog circuits on a die, to use transistors to bias the amplifier transistor. Once we switch from using a passive device like resistors for biasing to an active device like a transistor, we then can move to biasing transistor circuits with current courses, rather than resistors and voltage sources. (We still need power supplies.)

Lab exercises:

MOS transistor as a current source

A MOS transistor is a current source. If we look at the simplest model for an NMOS transistor in saturation (Full inversion, long channel length), we can see this:

The current is controlled by the difference between the gate to source voltage and the threshold voltage.

Figure 22: LTspice schematic that generates ID vs. VDS with VGS as a parameter for the ALD1103 CMOS chip.

Figure 23: ID vs. VDS with VGS as a parameter for the ALD1103 CMOS chip.

Figure 24: ID vs. VDS with VGS as a parameter for the ALD1103 CMOPS chip, on saturation shown demonstration that a transistor is a voltage controlled current source.

The circuit shown in Figure 22 was used to generate the waveforms in Figure 23 and Figure 24. We can see that in Figure 24, the transistor in saturation behaves as a voltage controlled current source as long as the circuit remains in saturation.

If we look at Figure 23 and Figure 24, we can see that the transistor based current source is not ideal because there is a slight rise in current as VDS is swept. All real current sources have a parallel impedance. This, just like all real voltage sources, have a real series impedance that we tend to ignore.

Figure 25: Graphical transformation of a transistor being used as a current source.

We saw that, in EE122, the output resistance of a transistor sets the upper limit of the gain of a CS amplifier and is given by . This implies that the more current that is used, the lower the output resistance and the less ideal a current source is. The parameter is a limiting factor in all analog transistor circuits, and many topologies are used to increase its effective value.

In LTspice, using NMOS and PMOS parts of the ALD1103. The sample starting file is located here. The EE122 lab manual is located here.

Extract VT, KN as shown here:

Use the file: to see how to create a file to extract these values.
Note 1: Read Amp1/2 from the right side of the graph.

Extract VA as shown here:

Use this file to see how to create a file to extract these values, but modify it to use the ALD 1103.

Note: The value of VA depends on the value of VGS, so you are really extracting an estimate of VA.

The data sheet for the ALD 1103 can be found here.

A clean version of the ALD 1103 chip package in LTspice can be found here.

Cascode circuits why:

We saw in EE122 that we used a “source degeneration resistor” to provide negative feedback to limit the variance in the gain of a Common Source transistor circuit caused by variances in the threshold and transconductance.

Figure 26: Generic Bias network for CS amplifier with source degeneration resistor RS.

Figure 26 shows a generic bias network for a CS amplifier. The resistor RS provides negative feedback that if allowed to go to infinity would completely negative the effects of a threshold voltage that varies.

The current is neglecting the Early effect. The voltage across is given by . The Voltage is set by a voltage divider or some other bias network and can be treated and an input.

Using Figure 26 and deriving for strong inversion, with no channel length modulation () we see that:

If we let :

Now, this might sound somewhat non-physical, because in the spice model we just used, not current flows when , but it is the same kind of approximation when we assume for an ideal OPAMP with feedback. The important thing is that with the larger the feedback resistor the value of becomes more independent of and . Transistors acting as current sources can act like a very large .

Cascode circuits: Use a MOS as a source degeneration resistor

To see how cascode and source degeneration affects a CS amplifier is the simplest manner one can sweep the input voltage and take the derivative of the drain voltage as shown in Figure 27. The link for the file is located here. Run the file and you should see Figure 28. Plot V(d), V(d1), and V(d2) to get XX. Then plot d(V(d)), d(V(d1)), and d(V(d2)) to get the gain in Figure 29.

Figure 27: LTspice circuit used to generate "Gain".

Figure 28: Drain voltage vs. input voltage for CS amplifier with no source degeneration (Blue), with Cascode degeneration (green), and resistor source degeneration (red).

Figure 29: Gain vs. input voltage for CS amplifier with no source degeneration (Blue), with Cascode degeneration (green), and resistor source degeneration (red).

One can see that the gain is reduced but more constant when source degeneration is used.

Cascode circuit reverse: Use a MOS as a current source load

Download this circuit and run. You should be able to see Figure 30 and plot Figure 31.

Figure 30: CS amplifier with PMOS load.

Figure 31: DC gains for CS amplifier with PMOS load (green) and resistive load (blue)

Report:

Repeat all figures and do all extractions and the derivation. (Do it for practice, not for documentation) There is no lab report due for this week’s lab. You will need the extractions for later.

Weeks 6 and 7: MOS current mirrors.

Introduction:

This week you will build and verify several current mirrors. You will use the ALD 1103 part which has two matched NMOS, and two matched PMOS transistors. The data sheet can be found here.

Current Mirror

Create a schematic in LTspice for the two current mirrors shown below in Figure 32. The starting schematic is located here. Use three values of RSET that different by three orders of magnitude such as 400, 4k and 40k Ω. You need to set up the Isource node to a voltage source and measure the current through it. A sample LTspice file for the NMOS current mirror can be found here. Measure the currents of both NMOS and PMOS transistor pairs and see how closely the currents match.

Figure 32: NMOS and PMOS current mirrors.

Build the two circuits and measure the two drain currents of each circuit. See how closely they match the hand calculation, Spice simulation, and your measured results.

Measure the output resistance of the current mirror:

For the same circuit, pick one value of RSET and measure IDM3 and sweep VLOAD from 0 to 5V and shown in Figure 33. You should see a figure like Figure 34, except this figure has three different RSETS. Plot the output resistance with this code 1/d(ID(M3)). You should see Figure 34. Notice how the larger the current, the lower the ROUT.

Build the circuit and step VLOAD from 0 to 5 in steps of .1 or .2 Volts. Plot in Excel or python and extract compare to simulations. This might be noisy as we are taking a derivative of a signal.

Figure 33: LTspice schematic of the current mirror to verify the Rout of the current mirror.

Figure 34: IDM3 vs. VLOAD to measure Rout of the current mirror.

Figure 35: Rout vs. VLOAD of the current mirror.

Current Source and Mirror:

Figure 36: Current Source and Current Mirror

Create and LTspice schematic of the circuit shown in Figure 36. Measure and compare the current through RSET and compare it to the current passing through the drain of Q4 for the same three values of RSET as you used in the previous section. Build the circuit and make the same comparisons.

Lab Report:

In the standard lab report format compare and contrast all theoretical calculations, LTspice simulations, and measurements. Use the data you extracted from last week’s lab to support your reasoning.

Weeks 8 and 9: Differential Pair.

Introduction:

OPAMPS are made up of current mirrors and differential pairs. In the previous labs, you built and tested current mirrors, which are a way to make current sources. To better explain why we use current sources/mirrors to bias the differential pair it seems best to start back with the common source amplifier, but instead of biasing with resistors, biasing a common source amplifier with a current source/mirror.

There could be some frustration when trying to model a circuit that has a current source. Sometimes when we model a current source in small signal analysis, we remove the current source because it is DC. (Like setting DC voltages to ground) Sometimes it is removed completely, and sometimes it is replaced with the output resistance of the current mirror (source). Sometimes we even remove the output resistance.

It might have seem like a distraction to go back and review CS amplifiers biased with current sources, but given that the current source significantly affects the gain in a differential pair, it is better to review this topic first. Please do not skip this section.

Common Source Amplifier biases with a current source

If we look at Figure 37, we see a common source amplifier biased with a current source rather than a drain resistor. The reason for this is that a resistor will have a voltage drop that is proportional to the current (), that limits how much ( in this case.) can swing. For more details see the EE122 lab manual. This can be seen in Figure 38: The larger the current, or resistance the larger the potential drop across the resistor. Notice that the current source gives the same current regardless of the voltage! This means the output voltage should be able to swing up to the power supply.

Figure 37: Common Source Amplifier biased with a current source.

Figure 38: Current vs. Voltage for an ideal current source (blue) and a 1k resistor.

Figure 39 shows the small signal model of a CS amplifier biased with an ideal current source. The gain of this can be shown to be:

This is because we have removed the current source because it is DC and the output resistance of the current source because it is ideal. The simulation results can be seen in Figure 40, and that the gain matches the equation.

Figure 39: Small-signal model of a common source amplifier with an ideal current source as a load.

Figure 40: Output of a small signal model of a common source amplifier biased with an ideal current source.

We need to verify this with a large signal model. If we sweep of Figure 37 and plot and then take the derivative of we will be able to see what the DC offset and gain will be at that bias point. The result of this can be seen in Figure 41.

Figure 41: Output vs. input voltage and gain for a CS amplifier biased with an ideal current source. (NMOS transistor ALD1103)

There are several problems with these results. The first is that the output voltage goes above the power supply which was 5 volts in this case. This happens because ideal current sources raise the voltage until the correct current is attained. The current sources we are using, in this case, are acting as a load and thus have a voltage limit. The second issue is the range of constant gain from seen in Figure 41. The constant gain is caused by the ideal current source that was used in Figure 37. (The gain does not match the small signal analysis because the small signal analyses used different conditions.)

These issues can be fixed by setting the current source to be a load as seen in Figure 42. To set a current source as a load, edit the current source and select load as in Figure 43.

Figure 42: CS amplifier biased with an ideal current source that is set up as a "load".

Figure 43: Setting a current source to be a load.

Figure 44: Output vs. input voltage and gain for a CS amplifier biased with an ideal “load” current source. (NMOS transistor ALD1103)

Looking at the results in Figure 44, we see that the output voltage does not go above the power supply and that the gain is about the same, which is ~160, for a small range of input voltage.

Ideal current sources and even ideal currents sources that act as a load do not exist in the real world. They all have a finite output resistance and limited voltage range.

Figure 45: CS amplifier biased with a series of NMOS and MOS current mirrors.

Looking at Figure 45, we see that the drain current of MG is set by R1 and a voltage supply. The diode-connected transistor M6 causes a voltage that biases transistor M7, which acts as a current course for the diode-connected transistor M1, which causes a bias voltage for transistor M3 which is the actual current source I2 from Figure 42! It would have been possible to use a set resistor for M1 directly, but we will need a bias point for both N and PMOS transistors later. Note that in this example, 4 transistors are used to make the current source. If we used cascade current sources, there would be more. Authors of journal papers and textbooks on analog design assume that you know this. Whenever to see a current source, know that there are current mirrors made out of transistors that are used to create it.

Figure 46: Output vs. input voltage and Gain vs. input voltage for a common source amplifier biased with realistic current mirrors. The bias current is the same as the other examples, 949.57592µA.

Notice how the gain is reduced. This gain reduced is due to the finite output resistance that acts in parallel to the output resistance of transistor M2. This alters the gain equation to be:

Figure 47: LTspice file for CS amplifiers using the ALD1103 chipset.

The LTspice file for Figure 47 can be found here. Download the file and repeat the plots shown in this chapter so far. Then plot VOUT3 and VOUT4 and the gain. The gain ideal should be very close to 1, but there are issues. Explain what these issues are.

Plot VOUT5 and the gain. This is a PMOS CS amplifier with an NMOS current source load. Why is the gain different?

Download this file, and run in LTspice. This simulates a small input voltage sin wave. Verify that the gains match for VOUT, VOUT2, and VOUT5.

Introduction to the Differential Pair:

Even though replacing a bias resistor with a current source can increase the voltage swing of a CS amplifier there exists the DC offset problem. The gate voltage has to be set by resistors and input signals can only be added with DC blocking capacitors. This means the amplifiers cannot work at DC. The output voltage of the CS amplifier has two parts: the small signal (AC) and the DC offset. The DC offset has to be blocked before it can be processed to the next stage. (Sometimes this is called the common voltage.)

The differential pair amplifies the difference in voltage rather than amplifying one voltage measured with respect to ground.

One might think we can use two CS amplifiers and take the output as the difference of two drain voltages of M1 and M2. As shown in Figure 48. The “odd” results can be seen in Figure 49.

Figure 48: Badly formed differential pair.

Figure 49: Not a differential pair.

The reason this does not work is that the current between M1 and M2 are not related. To make them related, we have to add a current source connecting both the sources of M1 and M2 as shown in Figure 50. The spice file can be found here.

Figure 50: Resistively loaded differential pair.

Figure 51: Results of a resistively loaded Differential Pair.

In Figure 51, we can see that the gain is approximately 2 near VIN- of 2.5 volts. We notice that the voltage does not change except near the 2.5 voltage point. Interestingly the node CM is often set to ground when deriving the small signal the CM node voltage is not constant. We can set it to ground assuming the variation in CM voltage is small. It might seem that we are again stuck with needing a DC voltage and that the output voltages have a DC offset. Looking at Figure 52, one can see that even though have DC offsets, the difference between the two nodes does not. (It does have a small offset due to transistor mismatch and other things and is the source of the offset voltage VOS in an OPAMP.)

Figure 52: Differential voltage.

Figure 53: Differential Voltage and gain vs. input voltage with VB as a parameter.

Now, look at Figure 53. Notice that the differential voltage curve gets shifted to the right as VB is increased. We can control the spot where the maximum gain with a voltage.

Notice that the gain is small. If we increase the loads R's to increase gain, more voltage will drop across them, and at some point, the differential pair will not work.

Look at Figure 54(Spice file). We step the load resistor from 1k to 10K, and the gain should increase as RL is increased. We see in Figure 55 that it does but then some odd things happen to the gain. Solution: Use PMOS loads.

Figure 54: Differential pair with RL as a parameter.

Figure 55: Differential Voltage and Gain with RL as a parameter.

A realistic and straightforward MOS based differential Pair

Looking at Figure 56 we see a realistic differential pair (Spice file). M6 and M7 make the current mirror to provide the bias current. M1 and M3 are the PMOS Loads. (Please see text for explanation and derivation.) These transistors are loads, and they are a current mirror, but current flowing in M2 and M4 sets the current. This circuit also converts the differential voltage to a single-ended voltage while keeping the gain the differential gain or a regular differential pair. Looking at the output voltage and gain of the differential pair we see that the maximum gain point is moved by setting Vin- as a parameter. Note that at VB= 2.5 Volts, the gain is the same is as the CS amplifier form Figure 45 and Figure 46. Accepts the gain is positive. Notice that the gain is not the same at each voltage. The value to are seeing is the DC open loop gain of the differential stage of an OPAMP. This is why we cannot use the AVOL from an OPAMP in our designs; we have to design it away, as it varies with voltage as well as from chip to chip.

Figure 56

Figure 57: Simple realistic Differential Pair.

Figure 58: Output voltage and gain of a differential pair with Vin- as a parameter.

A simple application of this would be as a comparator. If the voltage is above Vin-, then the voltage output is high, else it is low. There is a problem with this. The low voltage is not close to zero. To fix this, we put a PMOS CS amplifier on the output as shown in Figure 59. M8 is a PMOS that in this case is not the load, but the amplifier. M5 is the current source, which is biased by the diode-connected M6 transistor. Note that because the CS stage that is added is an inverting stage, we have to switch the labels of VIN+ and VIN-. The results can be seen in Figure 60. Notice how the transitions are sharper, and the gain becomes more constant. It still does not go the positive rail of 5V, but fixing that is an advanced topic.

Figure 59: Realistic Comparator or two-stage OPAMP

Figure 60: Two-stage OPAMP used as a comparator.

For the Lab Report:

Build the circuit as shown in Figure 59, and test as shown in Figure 60, except you, only have to set VIN- to 2.5 Volts. Vin- can be set with a voltage divider. (It does not have to be exactly 2.5Volts.) You will need to sweep VIN+ however which needs another power supply, or you can use a voltage divider with one resistor as a potentiometer. It might be possible to use the function generator for Vin + and use a triangle wave for 0 to 5 volts. Then use the x-y function of the scope and math to get Figure 60. It might be too noisy. Measure the voltage at which the output goes from low to high and compare that to VIN-. Explain any differences between LTpsice and measured results. Measure the gain and compare it to spice and theoretical calculations. You will have to measure Rout or VA for the NMOS and PMOS transistors. Do not disassemble this circuit as you will need it later.

Input a square wave from 0 to 5 volts with a frequency of 100Hz and a duty cycle of 50%. Compare LTspice simulation (Voltage Vs. time ) and what you measured and explain any differences.

Video on testing differential pair.

Video scope and function generator

Video Extracting Diode parameters

Figure 61: Measured results for the comparator. Gain approximately 400.

Figure 62: Vout vs. Vin, Trip pint very close to 2.5 Volts.

Week 10 and 11: High-Frequency Modeling of MOSFET amplifiers

Introduction

In prior classes whenever we have designed a common source amplifier, we “short” the capacitors that block the DC signals. This is because the DC blocking capacitor, C3 forms a high pass filter with R1|| R2. If we look at just at the small signal model of the input part of Figure 63, (Assume no current flows into Gate of MOSFET) we get Figure 64. Figure 64 shows two models of the high pass filter and the transfer function of a circuit that checks to see if the model matches theory. Figure 65 shows that all three-output match and that for frequencies higher than 10Hz that gain is 1 V/V and the phase delay is 0o.

Figure 63: Common source amplifier.

Figure 64: AC model of high pass filter formed by C3, R1, and R2.

Figure 65: Bode Plot of AC model of high pass filter formed by C3, R1, and R2.

We also “short” the source resistor because the equivalent impedance of RS and C2 is given by:

For large Frequencies:

, which goes to zero for high frequencies.

Which is about 63 and when compared to 249k of the drain resistor, it appears that the source resistor is effectively shorted at AC (small signal analysis.)

Finally the output coupling capacitor C1 and RL make a high pass filter with , which blocks the DC offset from the transistor bias circuit. While it is true that the use of PMOS current mirrors would reduce the amount of DC offset, the DC offset still needs to be filtered out before the next stage.

The net result of this is that for signals above 10Hz there is no phase shift or attenuation due to the coupling capacitors, which is why for small signal analysis, we short these coupling capacitors.

What would happen if the coupling capacitors were smaller? The cut of frequency would increase, and the frequency range of the amplifier would be reduced. While it is true we can select the value of these capacitors so that this does not happen, there are capacitances associated with the transistor that are small, and cannot be "shorted" for small signal analysis.

Looking at Figure 63, there are three coupling capacitors, and five NMOS capacitors, COX, GDB, CSB, CGD, and CGS. That means 8 energy storage elements, but as configured GGS0 and COX are in ||, so it is seven energy storage elements, which confirms the order of the system.

The capacitances for an NMOS transistor are given in Figure 66:

Drain to Body (PN junction)

Sidewall junction not under the gate (CJSW, MJSW, PBSW in this model no difference)
Sidewall junction under the gate (CJSW, MJSW, PBSW)
Bottom junction (CJ, MJ, PB)

Source to Body (PN junction)

Sidewall junction not under the gate (CJSW, MJSW, PBSW in this model no difference)
Sidewall junction under the gate (CJSW, MJSW, PBSW)
Bottom junction (CJ, MJ, PB)

Drain to Gate (Oxide, overlap) (CGDO)
Source to Gate (Oxide, overlap) (GGS0)
COX (The actual MOS capacitor) (COX)

The text should have a picture of what these mean.

Figure 66: Spice model of 2N700NMOS transistor. W=1600μm, L=4μm

These capacitances cannot be ignored at higher frequencies.

If we run an AC spice analysis on the amplifier as shown in Figure 63, we see the "bandpass like" features of the CS amplifier in Figure 67.

Figure 67: Bode Plot of CS amplifier using a 2N7000.

We see that form about 100 to 100kHz the gain is 36dB or approximately 65V/V, and the phase is , which makes sense because this is an inverting amplifier. The phase does not look high pass filter like below 1Hz, and the frequency response is really strange at frequencies that are so long it would take too long to measure so that we would ignore it. How long would it take to measure one cycle of a 10mHz sine wave?

The magnitude starts to drop off at 1MHz and settles at 0dB near 1Gz with a phase of which indicates there are at least 4 poles. This is tricky because it also looks like there are three zeros, and a phase shift of . This would indicate that there are 4 more poles than zeros. This implies that there are three zeros and 7 poles, which would be a 7’th order circuit. The fact that the gain flattens out at high frequencies means that there are some zeros which would cancel the downward trend caused by the poles. It seems like a conflict, would mean there are 4 more poles than zeros, but the number of active poles and zeros have to be equal for the gain to be flat. The trick is that a zero on the right-hand plane causes a negative phase. The zero on the right-hand plane is caused by the negative feedback of the capacitor from Drain to Gate. This zero in the right-hand plane is what can make OPAMP unstable.

Looking at Figure 63: Common source amplifier., we can see there are three coupling capacitors and five capacitors due to the MOSFET (COX, CGD, GGS, CDB, CSB). This simplifies down to three capacitors, because as configured the CSB is shorted, and COX and CGS are in parallel as can be seen in Figure 68. We can see that the Bode Plot at above 10Hz matches very well with the Bode plot of the LTSpice model. One thing different is the phase. Sometimes LTspice will put phase as phase. To fix this just plot –V(d) as in Figure 70.

Figure 68: High-Frequency models of CS amplifier.

Figure 69: Bode Plot of high-Frequency models of CS amplifier.

Figure 70: Modified Bode plot to show phase properly for CS amplifier.

The other difference is that the high-frequency Gain from the LTspice model flattens out to 0dB, while the small signal model flattens out to -28dB.

If you want to model the effect of the combination, add it back in as in Figure 71, with results shown in Figure 72.

Figure 71: Schematic the effect of the source degeneration resistor and shorting capacitor.

Figure 72: Bode Plot with the effect of the source degeneration resistor and shorting capacitor.

For the Lab Report:

The sample LTspice file is here. Create the schematics and Bode plots from this chapter and derive the gain vs. frequency response. You can try to see if the miller approximation works. See how it compares to the Bode plots. Build the circuit from Figure 63 and create a bode plot.

Note you cannot use a 1V AC signal. Even a 10mV is too large. 1mV Peak to Peak will be ok. You will have to use a voltage divider to get the input that small.
Of course, you cannot go up into the GHz range with our test equipment (10MHz). After this is done, build the circuit shown in Figure 73. Test it with a Bode Plot as well. Compare a theoretical model with LTspice, and what you measured. Explain all results.

Figure 73: CS amplifier with a Cload of 100p

Figure 74: Bode Plot with a CLoad of 100pF

Week 12: OPAMP Bias and Compensation Design

Introduction

As you are aware, OPAMPs have many different properties that you can find in the datasheet, such as . These values are a direct consequence of:

Size of the transistors (Length, Width, Area).
Type of transistor (MOS, BJT JFET).
How they are connected (what kind of current mirror topology)
Bias current
The RC network between the output and the inverting terminal of the input differential pair. (Capacitor value and how it is connected.)
Number of stages
Temperature, power supply

Here is a PPT file showing the design flow of a two-stage CMOS OPAMP using the ON-SEMI process. You will make a two-stage OPAMP using the ALD1103 chips set, using the same topology. Since the widths and lengths of the transistors are fixed, you control the input bias current, and the compensation capacitor and resistor. After measuring the offset voltage and , and verifying your design is stable, you will use it along with a driver stage to make an audio amplifier.

Design Equations:

Figure 75: Two-stage CMOS OPAMP

Transistor	Type/Function	Bias Current into M6(IB)
M1	PMOS, “Load” for differential pair
M2	PMOS, “Load” for differential pair
M3	NMOS, gain transistor for differential pair
M4	NMOS, gain transistor for differential pair
M5	NMOS, current source for differential pair
M6	NMOS, Diode connected voltage generator for the current mirror
M7	PMOS, gain transistor common source second gain stage
M8	NMOS, current source load for common source second gain stage

The gain of the differential pair is given by ():

The gain of the common source second stage is:

The total gain of the two-stage OPAMP is:

The Gain Bandwidth is given by:

This equation is not perfectly accurate. It is used to help tune the value of to make the OPAMP stable.

The value for is given by:

Again, this value is not entirely accurate. You will “tune^[1]” and to make your OPAMP stable.

Constants Depend on Bias Current:

The bias current which is the first design parameter you choose affects of both stages and the of each transistor. While the equations (full inversion) for these values can be calculated from a table of “constants”, and the results you will get will be correlated with LTspice, or measured results, they can be off by more than 20%^[2]. If you extract of both stages and of each transistor at the bias current that you have selected, then the gains will be very close to LTspice. Since transistor parameters can vary with fabrication runs, measured results will still be off from theory. As long as the is times the gain of your application, and the is high enough not to affect your application, and the OPAMPS is stable, it is OK that your hand equations did not match. (Still, you might want to see what is going on.)

Design methodology:

This is a simple summary of the design mythology. A case study will be presented.

Choose OPAMP topology.

How many stages, current mirrors, fully differential, output stage.

Find/choose transistor dimensions

In this lab, they are chosen for you because we are using the ALD1103.
This is beyond the scope of this class

Use gm/id to avoid sub-threshold

This advice is to make sure the offset voltage of the differential pair is minimized. This might not be good advice in all cases.

Chose bias current based on gm/id
Re-simulate gm/id for VSB not equal to zero, find

Ro, gm, estimate gain.

Verify DC gain (Is it good enough for our application?)

Make sure step size is small enough to measure the gain.

Simulate frequency response

First pass without and
Second pass add a compensation capacitor, without based on GBW equations and a goal of using LTspice. Might take a few runs to get close.
Final pass add based on equation. If the peak is too high, reduce. If the phase is too high, increase

Verify compensated design for integrator and buffer
Measure VOS, and AVOL in LTspice using sample circuit.
Estimate the minimum R-value that can be driven. Rload’s below 50k can be problematic
Monte Carlo to see a range of variance the circuit can take. (Not part of this course.)
Fabricate, test, write datasheet, form company to sell.

Pay a professor to be on the company’s board of directors.

Case Study 2-stage OPAMP gm/id full inversion Design:

All the LTspice files can be found in the zip file.

Extracting gm from a gm/id plot for the differential pair transistors (M3, M4):

First, we use the gm/id method to select a full inversion bias current. The NMOS transistor shown will be used to extract the values of and of the NMOS differential pair.

Figure 76: LTspice schematic (Link) used to extract intial gm/id plot. IBias=0A, so VSB=0V.

Figure 77: Initial gm/id plot, set IBias=0A, so VSB=0V.

For this example choose 10mA for the bias current.

Figure 78: LTspice schematic (Link) used to extract the gm/id plot. IBias=10m (Power supply changed to .)

Figure 79: gm/id plot for NMOS differential pair (M3 and M4), set IBias=10mA.

At 10.052mA, ,

This means (from Figure 75).

Extracting Rout for the differential pair transistors (M3, M4):

Figure 80: LTspice schematic (Link) used to extract . Extract at IB=10mA

Figure 81: Find Voltage to read the value of . (9.1V) (from Figure 80.)

Figure 82: Rout for M4 extracted at 9.1V ()

Extracting Rout for the current mirror load of the CS stage (M8):

Figure 83: LTspice schematic (Link) to extract Rout for M8 of the current mirror load of the CS stage of the OPAMP.

Figure 84: Rout for M8 extracted at 20mA.

Extracting Rout for the PMOS loads for the differential pair (M1, M2):

Figure 85: LTspice schematic (Link) to extract Rout for M2 of the load of the differential pair stage of the OPAMP.

Figure 86: Rout for M2 extracted at 10mA.

Extracting Rout for the PMOS amplified of the CS stage (M7):

Figure 87: LTspice schematic (Link) to extract Rout for M7 CS gain stage of the OPAMP.

Figure 88: Rout for M7 extracted at 20mA.

Extracting gm for the PMOS CS stage (M7):

Figure 89: LTspice schematic (Link) used to extract the gm/id plot. IBias=20mA (Power supply changed to .)

Figure 90: gm/id plot for PMOS CS gain stage (M7), set IBias=20mA.

We have to extract gm at 20mA because the current is twice that of the differential pair. One could change this by adjusting the widths. Since we are using the ALD1103, we cannot control the transistor dimensions.

Calculating the DC gain of a two-stage OPAMP):

Table 1: Design Values, IB=10mA, IB2=20mA

Variable (units)	Value
()	8.8
()	11.18
	97
	107
	67
	59.6

The gain of the differential pair is given by ():

The gain of the common source second stage is:

The total gain of the two-stage OPAMP is:

Verifying the DC gain with a DC sweep:

Figure 91: LTspice schematic (Link) used to DC gain from a DC sweep of uncompensated OPAMP.

Figure 92: DC gain of differential pair (-496).

Figure 93: Gain of OPAMP. Too small step size too big (gain is only 8k vs. 167k)

Figure 94: Gain now 203k

Figure 95: Gain of PMOP CS stage -417

Table 2: Comparison between Theoretical and extract gain of two-stage OPAMP

	Theory from extracted gm, Ro values	Extracted from DC sweep	% Relative Error
Differential Pair Gain	-448	-496	-9.68
CS Gain	-372	-417	-10.798
	167k	203k	-17.738

If we look at the range of the various transistors, it can be seen that Rout is very sensitive to the exact value of bias current. We can rerun the DC sweep to see what the currents going through M2, M4, M7, and M8 were and extract gm/id and Rout and see if the values match more closely. Rather than do this, it is better to realize that slight changes in bias current can cause significant shifts of OPAMP parameters such as .

Figure 96: Drain currents for M2, M4, M7, and M8.

Compensating the OPAMP with CC and Rz so the output will not oscillate:

Figure 97: LTspice schematic (Link) test bench to test the frequency response (AV(f)) of the OPAMP without compensation.

Figure 98: Frequency response of uncompensated OPAMP.

Looking at Figure 98, one can see that the . The phase at the GBW point is which is more negative than . This means that when the OPAMP is configured with negative feedback, there will be positive feedback. This can make the output oscillate, like the LT1307 example at the beginning of the 124 lab. Even if the phase as larger than , it could still oscillate when driving a capacitive load. Note: The term used when using phase to discuss control is phase margin and is usually done with absolute value:

In this case:

A negative phase margin means that there will be positive feedback when you wanted negative, and the circuit will be out of control.

To fix these issues, we add a capacitor between the output and the drain of M4 of the differential pair.

We will add a zero canceling resistor as well, but first, we use a capacitor.

Find a starting point for the CC using the following equation:

Do not use the 325MHz gain bandwidth. Go back to your BODE plot and select a frequency that has a phase between . (Figure 99)

Figure 99: Bode Plot showing desired GBW of 1MHZ (Phase=-90.480).

GBW desired is 1MHz, which would give us a phase margin of .

1.4nF

While this is OK for our design, that size of the capacitor would take up too much area. We can use a phase margin of . To get the frequency with a phase margin of read the frequency that corresponds with . In this case, the GBW that is desired is 9MHz. This gives a value for .

Figure 100: LTspice schematic (Link) test bench to test the frequency response (AV(f)) of the OPAMP with compensation capacitor only.

Figure 101: Bode Plot showing desired GBW of 12MHZ (Phase=-1480) due to a feedback capacitor.

While adding a feedback capacitor helped increase the phase margin to , it is not enough to create a design that will be stable. To increase the phase margin (decrease the phase at the GBW point), we add zero cancelling resistor:

Figure 102: LTspice schematic (Link) test bench to test the frequency response (AV(f)) of the OPAMP with a compensation capacitor and zero canceling resistor (RZ).

Figure 103: Phase has a hump near 100MHz.

Looking at Figure 103. There is a hump near 100MHz, that will cause control issues. To make the hump go down decrease Rz. In this case, try 100pF.

Figure 104: Frequency response of an OPAMP compensated with a 156pF feedback capacitor and 100 zero canceling resistors.

Figure 105: LTspice schematic (Link) wit CC=156pF, and Rz=100 Gives GBW of 8MHz with a phase of -92o for a phase margin of 88o.

Applications for the OPAMP:

To use the OPAMP in an application, one has to create an application note or data sheet just like an application engineer would. You will extract the offset voltage, DC gain, and GBW. Some of these circuits you have used before to make things easier an OPAMP with a symbol has been created. The downside is that you have to download a zip file to use it. The zip file for all the circuits uses in the above, and the circuits we will use for extraction is located here. The part number is SJSU1006.

VOS:

Figure 106: LTspice schematic of the circuit used to measure VOS and DC gain. (AV_VOS.asc)

There are two ways to use the circuit shown in Figure 106. The first way is to set V3=0V and use a standard voltmeter to measure the voltage at node Vos. Divide this voltage by 1001 to calculate the value for the offset voltage. The second method is to use a sin wave with an amplitude of 2V or 4V Peak to peak and a frequency of .1 to 1 Hz. A .1 Hz signal takes a long time measure, but a 1Hz Signal might be attenuated. An AC simulation of the circuit indicates that the circuit should work with sin waves of 3 Hz or less. A different OPAMP might behave differently. To see the extracted offset voltage, click on View… Spice error log. Scroll down in the pop-up window to see the results (Figure 107).

Figure 107: Results of VOS extraction.

DC Gain:

Figure 108: LTspice schematic of the circuit used to measure the DC gain (AV_VOS.asc)

Figure 108 shows the circuit used to extract the open loop gain of the OPAMP (AV, or AVOL)

This is the same circuit that is used, and the gain can be measured at the same time using an oscilloscope. Measure the peak to peak voltage of V3 and the peak to peak voltage of VOS, while measuring the average voltage of VOS. The spice error log has both values as shown in Figure 109.

Figure 109: Results of AVOL extraction.

This OPAMP does not have a current drive stage (common drain), and so the gain will be sensitive to driving a load resistor.

Figure 110: Circuit used to measure VOS and AV with a load Resistor.

Figure 111: AV vs. RL.

Figure 112: VOS vs. RL

GBW:

Figure 113: Circuit used to measure GBW (GBW.asc)

The resistor is required to make sure the input voltages are almost equal, and the capacitor is used to block DC signals. The downside is you do not get a bode plot that looks like a bandpass.

Figure 114: Measuring GBW with a two-point extraction.

If we look at Figure 114, there are two points (~1kHz, and ~100kHz) being used to extract the GBW. The problem with using a sin wave at 1kHz to test that point is that the Gain is 77dB. Given that the smallest signal from the function generator is 20mV, the output would be which is larger than the power supply. One could use voltage division to bring it down, but it would be better to use a gain of around 50dB. (In this case, 25kHz gives approximately 50dB, with a phase of nearly 90o. ) The issue with 100kHz is that a proto-board might cause issues with the measurement. Once you have two points, create a function for the line, and find where the lines reaches zero. This is your GBW. You should get a value from LTpsice close to 8MHz.

Application 1: Buffer

Figure 115: LTspice schematic of SJSU1006 OPAMP configured as a voltage buffer. (buffer.asc).

Looking at Figure 116 and Figure 117, there is no evidence of peaks in the frequency response or ringing in the step response, so the OPAMP is compensated. Adding a capacitive load will reduce the phase margin and at some point if the load capacitor is large enough ring will occur.

Figure 116: Frequency response of SJSU OPAMP configured as a voltage buffer.

Figure 117: Step response of SJSU1006 OPAMP configured as a voltage buffer.

Application 2: Integrator

Figure 118: LTspice schematic of the SJSU1006 OPAMP configured as a Deboo integrator. (Deboo.asc)

The transfer function of the circuit shown in XX would be if the OPAMP were ideal. In can be seen in Figure 119 that the circuit behaves according to this transfer function between 10mHz and 200kHz. A finite AVOL causes the error near DC, and GBW limitations cause the errors above 200kHz due to poles and zeros of the OPAMP's complete transfer function. The circuit can be seen to be integrating constants into linear functions in Figure 120.

Figure 119: Frequency response of SJSU OPAMP configured as a non-inverting integrator.

Figure 120: Square wave response of SJSU OPAMP configured as a non-inverting integrator.

Final Parameter for SJU1006 OPAMP:

Table 3: OPAMP Data sheet for SJSU1006.

OPAMP Parameter (units)	Value
AVOL (V/V)	Greater than 100k if RL>30kΩ 10k if RL=2kΩ
GBW (MHz)	8
Voffset (mV)	Less than 2.5 for 2kΩ< RL<200kΩ
Current Draw (mA)	60
Power Supply (V)	±10

As can be seen in Table 3, the OPAMP uses a significant amount of current. This was done on purpose to show what a full inversion design would look like.

Design an OPAMP:

All the design files can be found in this zip file.

Reduce the current draw:

Using moderate inversion or slightly full inversion to design you own OPAMP.

Choose the bias current,
Choose voltage supply,
Estimate gain and verify in LTspice with DC sweep.

Compensate your OPAMP

Choose/design CC.
Choose/design RZ.
Verify with LTspice
Estimate GBW in LTspice.

Build and test OPAMP

VOS
AVOL
GBW
Verify with buffer application.

Design a circuit using your OPAMP to drive a 4 or 8 speaker.
Build, test and document your design.

[1] In this case tune means guessing values and running LTspice to see if you are hitting your stability criteria.

[2] Wrong