Jarrett Minton

(435) 531-3737 | jarrett@cs.utah.edu | www.linkedin.com/in/jarrettminton

Education

• PhD in Computer Architecture from The University of Utah                             Aug 2023 - Current
• BS in Computer Science from Utah Valley University                          Aug 2018 - May 2023

Publications

ASPLOS ’25 *Distinguished Artifact Award:  

Jarrett Minton and Rajeev Balasubramonian. 2025. FlexProf: Flexible, Side-Channel-Free Memory Access.  

Research 

The University of Utah - Salt Lake City, Utah                                                                          Aug 2023 - Current

• Project 1:  Designed FlexProf, a side-channel-free DRAM memory controller that uses application profiling and opportunistic read and write turns to close timing leaks while improving performance by upwards of 33%; published at ASPLOS 2025.

• Project 2: First author under-submission work on browser side-channels showing that the state-of-the-art obfuscated-timer defense (Cook et al., ISCA'22) still leaks enough signal for a targeted ML binary classifier to fingerprint sites with up to 94% accuracy; stress-tested leakage with a pairwise analysis classifier over 4,950 site pairs and traced it to coherence traffic, motivating memory-hierarchy isolation as the next required isolation primitive.  

• Project 3: Ongoing first author work on side-channel-free memory controllers: extending prior secure defenses from DDR3 to DDR4/DDR5, along with a co-designed address mapper and a memory-side prefetcher that reclaims the schedule's wasted throughput without leaking side-channel information.

• Project 4: Co-author on ZKP acceleration hardware work; built Python simulations of prior-work architectures as baselines to benchmark our new design against on throughput and efficiency.

Work History

Internship 2: AI HW/SW Co-Design Intern - Ampere - Portland, Oregon                 May 2025 - Aug 2025

• Profiled GPU workloads on pre-release NVIDIA hardware using Nsight Compute (NCU) and Nsight Systems (NSYS) to benchmark hardware-level and system-level performance to prepare for Ampere's competing platform.
• Assisted in identifying performance bottlenecks to inform Ampere's competitive HW/SW co-design decisions.

Internship 1: LLM HW/SW Co-Design Intern - Ampere - Portland, Oregon             May 2025 - Aug 2025

• Simulated optimizing Large Language Models (LLMs) / LLama for high-core count Ampere ARM CPUs using differing HPC strategies.
• Lead the development and CI/CD of a new graph algorithm tool using Python/Graphviz/PyTorch for the LLM optimizations.

Teaching Assistant - Utah Valley University - Orem, Utah                                              Jan 2021 - May 2023

• Held office hours and graded for Computer Architecture, Data Structures and Algorithms, Programming Languages, Advance C++, Advance Python and more.
• Selected as TA Lead to mentor all TAs, providing structured feedback on grading and instruction techniques.

Service

ISCA’24 Artifact Evaluation Committee

University of Utah Graduate Student Advisory Committee, New Student Coordinator, 2023-2025