TrueAdapt™ to Enable Fine-Pitch Wiring on Flexible Fan-Out (FlexTrate™)

Fan-out-wafer-level-packaging (FOWLP) and fan-out-panel-level-packaging is an attractive cost-effective packaging platform that offers significant cost savings as compared to similar bridge connection technologies or interposers. Due to die-placement error and shift during molding, die assemblies on FOWLP can have significant die-shift. Design rules must ensure the accommodation of die-shift and as a result fine-pitch patterning is limited. TrueAdapt™ aims to solve that by utilizing in-line characterization of the die shift, generation of a new layout using the measured offsets, and patterning with direct-write lithography for high throughput wafer-level and panel-level fabrication at fine-pitches. We have fabricated an assembly of dies interconnected in a daisy chain network with 10 µm pitch wiring on the FlexTrate™, a bio-compatible polydimethylsiloxane (PDMS) based FOWLP architecture. We measure die shift using optical metrology techniques to generate a stitched image of the assembly. The image is then processed using computer vision to measure the die-shift. Furthermore, we generate a layout based on measured die-shift that adaptively routes the wiring in between dies. Via and metal layers are subsequently patterned using direct-write lithography using a 405 nm laser direct-write lithography system. Fan-out packages in addition to die-shift suffer from excessive warpage of the substrates. We have applied focus drilling to direct-write laser lithography, in a process we call Focal Extension, to extend the depth of focus (DOF) of our system to pattern over 100 µm of topography within a single field, making this a truly adaptive patterning process.

PhD student: Golam Sabbir, Henry Sun

Masters student: Mansi Sunil Sheth

Undergraduate student: Travis Ha

Image depicting the adaptive patterning employed in TrueAdapt™ (Left), Methodology of TrueAdapt™ (Right)

Animation showing how a high resolution image of a fabricated assembly is processed and digitized into a GDS

High Bandwidth Flexible Connector (FlexCon) for Large Area Computational Systems

Wafer-scale systems such as the Silicon Interconnect Fabric are capable of providing immense internal compute and memory bandwidth. However, for these systems to efficiently communicate with the external world we need novel connectors which have high energy efficiency and bandwidth, while also being flexible and compatible with silicon integration. FlexCon is being developed to address these challenges, and features > 240 Gbps/mm bandwidth, a highly flexible PDMS substrate, and solder- or TCB-based integration. Additionally, the fan-out wafer-level fabrication process enables embedding devices into the PDMS substrate, such as redrivers or retimers to extend the connector reach.

PhD student: Randall Irwin

Photograph of FlexCon (left) and micrograph (right) showing embedded devices.

Flexplay: Flexible MicroLED Display enabled by FlexTrateTM

We use the FlexTrateTM process, a Polydimethylsiloxane (PDMS)-based die-first fan-out wafer level packaging (FOWLP) platform to integrate GaN μLEDs (30μm x 30μm) with passive and driving components to build a flexible monochrome UV Micro-LED display. As the size of microLEDs decreases, there are many challenges associated with the transfer of these LEDs from their native substrate to a display-compliant substrate (in our case, a flexible substrate) including higher costs, lower alignment tolerances, and lower throughput. In our fabrication of a flexible passive-matrix display, we initially assembled a single monochrome array of near-UV GaN microLEDs directly on FlexTrateTM using a single novel mass transfer process based on adhesive bonding and laser lift-off. This method has very high transfer yields (>99.99%) and excellent scalability. We develop a two-level wiring scheme adapted from conventional silicon processing for our flexible substrates to realize the passive matrix LED array.

PhD student: Henry Sun

Figure 1

Display area: microLED array (30um x 30um) and CMOS LED Drivers (Left), Subpixels driven at 3.2V (Right)

Figure 2

Passive Matrix array: First level wiring addressing the N-contacts, Second level wiring addressing the P-contacts for the microLEDs.

Flexible Li-ion Batteries for wearable devices

Due to inefficient packaging and integration schemes, current power delivery systems for wearable devices have not advanced as significantly as device miniaturization, flexibility, and sensitivity. To address these shortcomings in power delivery, we propose a two-step approach:

Flexible Battery Fabrication

1.Battlet Design: This involves partitioning the cathode (LiFePO4) and anode (Graphite) films into an electrode array on flexible composite current collectors.

2.Interdigitated Design: This features cathode (LiFePO4) and anode (LTO/Graphite) films on coplanar interdigitated evaporated current collectors.
Using these designs, we fabricate flexible Li-ion batteries on biocompatible polydimethylsiloxane (PDMS) substrates and test their mechanical and electrochemical performance. We assemble the battery using the ionic-liquid electrolyte making it non-flammable, ensuring operational safety, which is critical for medical-grade wearables.

System Integration

We integrate the flexible battery module with a flexible wireless charger and a UV microLED array, employing Flexible Fan-Out Wafer-Level Packaging Technology (FOWLP).

This comprehensive approach offers a promising pathway for flexible energy storage and charging solutions. By combining high performance, safety, and form factor advantages, it has the potential to revolutionize wearable and biomedical applications.

PhD Student: Guanqui Quyang, Mansi Sunil Sheth, Henry Sun

Figure demonstrating a) Battlet design cofacial flexibe Li-ion battery b) Interdigitated Coplanar flexible Li-ion battery c) Integration of flexible Li-ion battery with wireless charger and microLED using FlexTrateTM