SoC FPGAs I Final Project
To: Ross Snider
From: Louis Rosenblum
Regarding: SoC FPGAs I Final Project
Date: November 26th, 2019
The end-goal of this project was to design a functioning Arithmetic Logic Unit running on the fabric of the DE-10 Nano FPGA. This ALU receives two inputs A and B, uses a 3 bit opcode to perform an operation, writes to the resultant registers, and indicates status flags. The ALU’s functionality was demonstrated by booting the FPGA from an NFS kernel server, reading various operations from a C program, and outputting the results to a PuTTY terminal over serial.
The custom operation implemented for this project was logical shift left. The operation only used one operand, operand A. This utilized the VHDL ‘shift_left’ function. LSL is capable of producing a zero result, a negative result, but not an overflow for a 32-bit input.
Process that functions as a slave device. The only signal is the sensitivity list is the clock. When the process fires the slave either reads data from the master and writes it to a register or writes a register value to the master depending on the value of the read and write flags. The operand swap operation uses the slave device to write the new values of A and B into memory. The avalon slave is necessary so that the C program can write operand and opcode values into the ALU component and read the result and status registers back.
Process that chooses which datasets to write to the LEDs. The sensitivity list includes the clock, reset, and the four binary switch inputs on the FPGA. Everytime the clock goes high an if statement is used to check the two most significant bits of the switch array. Each of the four possible values is routed to a unique register. A second if statement checks the two least significant bits of the switch array to decide which 8 bits of the 32-bit word to show on the 8 LEDs. “00” routes the least significant 8 bits and “11” routes the most significant 8 bits.
The ALU process functions as the actual ALU within the ALU FPGA component. The sensitivity list includes register 2, the opcode register. Everytime the opcode is updated the process uses if statements to detect which operation to perform. All logic, casting, and simplification is performed inside the elsif statement corresponding to each operation. From the result comparisons are used to detect if the result is zero, negative, or took more than 32-bits to store and the status flags are updated accordingly.
This semester introduced booting the linux kernel on an external device using ethernet. I was also able to gain experience using Platform Designer within Quartus. Being able to use platform designer expands the possibilities I can synthesize for use on an FPGA and reduces the complexity of implementing them.