Project 1: Logic Gates

B441/E315, Fall 2018                                                        Version 2018.0

Due Date: Aug 31, 2018

Overview

Logic gates are the foundation of all computer systems. They allow for the application of logical processing to be mapped onto physical circuits. In this lab project you will design and implement a digital system that uses three basic logic gates: the AND gate, the OR gate, and the NOT gate.

This assignment is to design and implement a digital system with two inputs and three outputs:

Inputs:                  a, b

Outputs:               myAND, myNOT, myOR

The logic schematic of the digital system is given below.

 

Background

AND Gate

The truth table for a 2-input AND gate is:

 

A

B

Out

0

0

0

0

1

0

1

0

0

1

1

1

 

And is denoted by the following schematic symbol:

The verilog keyword is: &

OR Gate

The truth table for a 2 input OR gate is:

A

B

Out

0

0

0

0

1

1

1

0

1

1

1

1

 

And is denoted by the following schematic symbol:

 

The verilog keyword is: |

NOT Gate

The truth table for a 1-input NOT gate is:

A

Out

0

1

1

0

 

And is denoted by the following schematic symbol:

 

The verilog keyword is: ~

Assignment Description

Source Code

You can start with the Verilog program that we implemented in Project 0: Vivado Tutorial:

module top(

        input sw,

        output led

        );

assign led = sw;

endmodule

You will create a Verilog program named top.v.  To do so, you will need to modify P0’s top.v, and change the declaration of the input and output signals:

You also have to expand the assign statements. Instead of a single one (assign led = sw;) you will need three assign statements, one for each output signal. For example, the assign statement for the output myAND should be:

assign myAND = a & b;

On the left hand side of the assignment operator (=) there is the output signal (myAND). The expression on the right hand side (a & b ) performs logic AND operation between the signals a and b. The result of the logic AND operation between a and b, will be assigned to the output signal myAND.

In a similar way you will write assign statements for the output signals myOR and myNOT. Recall the Verilog logic operators are as follows:

Logic Operation

Verilog symbol

AND

&

OR

|

NOT

~

Note: when assigning to myNOT, you will have to use ‘a’!

 Constraints

The constraint file should create the following mapping of input and outputs to the switches and LEDs on the Basys3 board:

 

Output signal

Basys switch/LED

a

sw0

b

sw1

myAND

led0

myNOT

led1

myOR

led2

 

Here we can make use of the “Basys3_Master.xdc” file uploaded on the Google Drive.  It can be found under GoogleDrive -> Resources.

Copy the statements from the “Basys3_Master.xdc” file into your constraints file:

Make sure that you make the following changes to the statements:

In the end, your constraints file should look similar to this:

set_property PACKAGE_PIN V17 [get_ports {a}]

    set_property IOSTANDARD LVCMOS33 [get_ports {a}]

 

set_property PACKAGE_PIN V16 [get_ports {b}]

    set_property IOSTANDARD LVCMOS33 [get_ports {b}]

 

set_property PACKAGE_PIN U16 [get_ports {myAND}]

    set_property IOSTANDARD LVCMOS33 [get_ports {myAND}]

 

set_property PACKAGE_PIN E19 [get_ports {myOR}]

    set_property IOSTANDARD LVCMOS33 [get_ports {myOR}]

 

set_property PACKAGE_PIN U19 [get_ports {myNOT}]

    set_property IOSTANDARD LVCMOS33 [get_ports {myNOT}]

TestBench

You will also need to create a test bench called top_tb.v to test your code.  Remember to select “System Verilog” from the “File Type” drop-down menu. Again, hit “OK” if you get a module pop-up. You can use the following starter code:

`timescale 1ns / 1ps

module testbench;

 

        reg a, b;

        wire myand, myor, mynot;

        top top0 (

            .a(a),

            .b(b),

        .myAND(myand),

        .myOR(myor),

        .myNOT(mynot)

         );

        

        initial

        begin

        //your testcode here!

            $display("@@@Passed");

            $finish;

 

        end

endmodule

Your testbench should test all 4 possible input combinations of a and b, and test for the correct outcome for myand, myor, and mynot for each combination. Recall, you can use the following verilog line to test a signal:

assert( led == 0) else $fatal(1, "led==0 Failed");

If you fail to test all 4 possible input combinations, the autograder will detect it in the following step.  

Evaluation

The evaluation will have two steps, first submission of your source code and testbench to the autograder.  Second, you will need to synthesize your design, download it to the FPGA and do a demonstration for the TA.

Autograder

Using a web-browser, log on to: https://autograder.sice.indiana.edu.  Note that you must be on campus or using a VPN for this link to work.  


From here, you need to:

Demonstration

You will also need to implement your project on the FPGA and demonstrate it to the TA.  To do so, you will need to follow the “Hardware Synthesis”, “Programming the FPGA” and “Testing your FPGA” sections of Project 0, and then demonstrate your working system to the TA.  You will not receive full points until the TA as approved your demonstration.