Evidence of matrix multiplication coprocessor in the M1
Dougall Johnson, Github
https://gist.github.com/dougallj/7a75a3be1ec69ca550e7c36dc75e0d6f
M1 SSD speed testing
Howard Oakley, Electric Light Company
https://eclecticlight.co/2020/12/17/comparing-ssd-performance-between-t2-and-m1-macs-with-stibium/
Memory Fences on x86
Bartosz Milewski
https://bartoszmilewski.com/2008/11/05/who-ordered-memory-fences-on-an-x86/
Memory system mismatch and performance
Hector Martin, Twitter
https://twitter.com/marcan42/status/1328940799082569729
X86 emulation and memory barriers
Bruce Dawson, Random ASCII
https://randomascii.wordpress.com/2020/11/29/arm-and-lock-free-programming/
QEMU emulation performance on RISC (memory barriers and cache flushes)
Peter Maydell, Github
https://github.com/qemu/qemu/blob/master/docs/devel/tcg.rst
ARMv8 memory barriers
ARM Developer
https://developer.arm.com/documentation/100941/0100/Barriers
Intel TSO mode on M1
Rob Graham, Twitter
https://twitter.com/ErrataRob/status/1331735383193903104
Force TSO Mode on the M1
Saagar Jha, Github
https://github.com/saagarjha/TSOEnabler
Potential bugs on the M1
David Smith, Twitter
https://twitter.com/Catfish_Man/status/1326240343415808001
Linus Torvalds talking about how you could do TSO mode
Real World Tech
https://www.realworldtech.com/forum/?threadid=193883&curpostid=193937
Interview with Mark Himelstein, CTO of RISC-V
https://riscv.org/announcements/2020/06/welcome-mark-himelstein-risc-v-international-cto/
Interview with Anshel Sag, Moore Insight and Security
https://moorinsightsstrategy.com/anshel-sag/
Interview with Aakash Jani, The Linley Group
https://www.linleygroup.com/analyst_detail.php?Aakash-Jani-33
Apple building 5G modems
Mark Gurman
M1 Analysis and blog diagram
Andrei Frumusanu, Anandtech
https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive/2
Toms Hardware M1 everything we know
Michelle Ehrhardt, Toms Hardware
https://www.tomshardware.com/news/Apple-M1-Chip-Everything-We-Know
Re-order buffer description
RISC-V BOOM, UC Berkeley, Abraham Gonzalez & Jerry Zhao
https://docs.boom-core.org/en/latest/sections/reorder-buffer.html
Re-order buffer
Dr Susan Eggers, University of Washington
https://courses.cs.washington.edu/courses/cse471/07sp/lectures/Lecture4.pdf
One more re-order buffer
Dr Michael B. Taylor, University of California San Diego
https://cseweb.ucsd.edu/classes/fa10/cse240a/pdf/07/CSE240A-MBT-L13-ReorderBuffer.ppt.pdf
Apple M1 programming benchmarks
Suhun Han, Tech.ssut
https://tech.ssut.me/apple-m1-chip-benchmarks-focused-on-the-real-world-programming/
Qualcomm X1
Robert Triggs, Android Authority
https://www.androidauthority.com/arm-cortex-x1-vs-apple-1121289/
Out-of-order execution
Dr Yoav Etsion, ETH Zurich
https://iis-people.ee.ethz.ch/~gmichi/asocd/addinfo/Out-of-Order_execution.pdf
Dr Susan Eggers, University of Washington
https://courses.cs.washington.edu/courses/csep548/06au/lectures/introOOO.pdf
Last-level cache design
Kurt Shuler, Arteris, All about Circuits
Spectre and Meltdown
Nael Abu-Ghazaleh, Dmitry Ponomarev and Dmitry Evtyushkin, IEEE Spectrum
https://spectrum.ieee.org/computing/hardware/how-the-spectre-and-meltdown-hacks-really-worked
Extreme Tech on Single Core Performance
Joel Hruska, Extreme Tech
WCCFTech on same
Usman Pirzada, WCCFTech
https://wccftech.com/why-apple-m1-single-core-comparisons-are-fundamentally-flawed-with-benchmarks/
WebXPRT Test
https://www.principledtechnologies.com/benchmarkxprt/webxprt/