All current development is on the MiSoC based  firmware.

This document is obsolete 
(as of 2015-12-01) and for the old Jahanzeb firmware.

See the “History” section of the HDMI2USB.tv website for more information.

        MITHIS

www.mithis.com

709,  243 Pyrmont Street

Pyrmont, NSW, 2009

AUSTRALIA

HDMI2USB

A HDMI/DVI Capturing Solution

Lead designer Jahanzeb Ahmad

Documentation by (Feel free to improve and add your name)

Jahanzeb Ahmad

Tim ‘mithro’ Ansell

General description

Atlys FPGA Board

IO connections

Status LEDs, Push buttons and Jumpers

Architecture

HDMI Matrix

EDID Hack

Flow chart of EDID Master

Flow chart of EDID Slave

Resolution Calculator

JPEG Encoder

Image Selector

Image Buffer

USB Top

Pattern Generator

Controller Top

// Edit by tija

Clock Domains of HDMI2USB

Building and configuration

Running of system

Webcam (UVC )

Serial Communication (CDC)

Components Address

USB Top commands

JPEG encoder commands

HDMIs

Source selector

RED, GREEN, BLUE commands

VGA daughter board commands(in progress)

Debug Module

Test setup

References and reading material

1. General description

HDMI2USB is a device to capture HDMI and DVI (and Displayport through cheap active adapters) and send it on USB port as UVC video. The device attaches computer as a standard webcam so there is no need of installing additional drivers. At the same time it also attaches to computer as a CDC serial device to communicate and check the status of different modules.

1. Atlys FPGA Board

Current design is based on Digilent Atlys board although custom device is under development. For more information on Atlys visit www.digilentinc.com/ATLYS/. LED4 - Flab C (Empty Flag) of cypress USB device.

LED5 - SLWR signal to cypress USB device.

LED7:6 - Combination of LED7 and 6 tells which input source is selected as output to HDMI matrix and USB.

1. IO connections

        Two HDMI inputs and Two HDMI outputs can be connected to the board. Output video is streamed on USB port using uvc. Same USB port is first used to program the device. see section 3 for more details. The diagram below shows the connections of HDMI and USB.

Status LEDs, Push buttons and Jumpers

LED0 - Indicates HDMI 0 input is connected.

LED1 - Indicates HDMI 1 input is connected.

LED2 - If on then UVC is MJPEG if off then output is RAW.

LED3 - Flab B (Full Flag) of cypress USB device.

BTNU - Selects HDMI 0 as output.

BTNL - Selects HDMI 1 as output.

BTND - Selects test pattern as output.

BTNC - If pressed emulates display connection to read edid structure.

Jumper J6 and J7 should be open to allow the EDID master slave to work properly.

Jumper J5, SCL and SDA should be close so that HDMI source can read EDID from FPGA.

2. Architecture

        The system is designed in VHDL and Verilog. Each component of the design is described in detailed. The block diagram of the system is shown in figure below.

2. HDMI Matrix

        ATLYS has two input ports and two output ports. The two output ports are identical and can be selected from either HDMI inputs either by CDC serial communication or by buttons BTNU and BTNL.  This module is modified version of Xilinx Application note xapp495 complete details of the implementation can be found on
http://www.Xilinx.com/support/documentation/application_notes/xapp495_S6TMDS_Video_Interface.pdf

3. EDID Hack

        EDID stand for Extended Display Identification Data. Used to identify capabilities of the display device using I2C bus. More information on http://en.wikipedia.org/wiki/EDID.

Edid hack is made of two components EDID Master and EDID Slave. EDID master reads the EDID structure from display device and EDID slave sends the appropriate structure to the computer based on the structure read from display device. If no display device is connected HDMI2USB sends EDID structure with resolution of 1024x768. Flow charts of the master and slaves are shown below.

Flow chart of EDID Master

Flow chart of EDID Slave

EDID hack is only used for HDMI 0, EDID Hack is not implemented on HDMI 1 because I2C pins for HDMI 1 on ATLYS are connected.

4. Resolution Calculator

        Resolution calculator calculates the resolution of HDMI inputs using rising edges of horizontal and vertical syncs. The resolution of the input HDMIs can be read from the system using reading the status of HDMIs.

5. JPEG Encoder

        An open source JPEG encoder from opencores is used in this system. Detailed information and documentation of JPEG encoder is available at http://opencores.org/project,mkJPEG. JPEG encoder is considered as a black box. A top module on black box is created consisting of a state machine to communicate with controller and USB data transfer. The state machine of the JPEG encoder top is shown below.

6. Image Selector

        Image selector selects the source for HDMI out and JPEG encoder or raw uvc output. It also processes the image data if required before passing it to HDMI output and image buffer for transfer it to USB ot JPEG encoder. The block diagram of the module shows the processing and selection of image data.

7. Image Buffer

        The image buffer stores the image into DDR2 ram on the ATLYS board. This module is composed of XIlinx MIG core, input fifo for data and two independent state machines. For more information on Xilinx MIG core consult ug416 and ug388 Xilinx user guide.

Write state machine is shown in flowchart below.

Read state machine is shown in the flowchart below.

8. USB Top

        USB Top is composed of a state machine and four sub modules each submodule has its own state machine. The block diagram of the USB top is shown in figure below.

9. Pattern Generator

10. Controller Top

// Edit by tija

Clock Domains of HDMI2USB

• clk: It is connected to 100MHz oscillator of the Atlys Board. This clock is input to the PLL in DDR2 controller which in turn creates clock signals of different frequencies.

• DDR2 Clock(sysclk_2x & sysclk_2x_180): Image Buffer of HDMI2USB works at 625 MHz
•  img_clk:  This clock signal is fed to all the other blocks of HDMI2USB except usb_comp. It is currently set to 78.125 MHz

To change the DDR2 Clock and img_clk, one has to change the following parameters in ipcore_dir/ddr2ram/user_design/rtl/ddr2ram.vhd

constant C3_CLKOUT0_DIVIDE           : integer := 1; --sysclk_2x = 625 MHz

constant C3_CLKOUT1_DIVIDE           : integer := 1;--sysclk_2x_180 = 625 MHz

constant C3_CLKOUT2_DIVIDE           : integer := 8;--img_clk = 78.125 MHz

constant C3_CLKOUT3_DIVIDE           : integer := 4;--calibration clock = 156.25 MHz

constant C3_CLKOUT4_DIVIDE           : integer := 25; -- ignore this

constant C3_CLKFBOUT_MULT            : integer := 25;--clk multiplier

constant C3_DIVCLK_DIVIDE            : integer := 4;--clk divider, so output =100*25/4=625

• CLK: (100MHz) This clock is also fed to test pattern generator, which uses DCM to generate a 65MHz pclk_tp clock.

Other clock signals:

• p_clk: pixel clock of the HDMI source
• pclk_tp : (65MHz) Pixel clock of VGA Test Pattern.
• ifclk : Input clock from the Cypress USB chip. It operates at 48 MHz.

3. Building and configuration

https://github.com/timvideos/HDMI2USB/wiki/Digilent-Atlys-Board%3A-Loading-Firmware

4. Running of system

bla bla...

11. Webcam (UVC )

        bla bla bla

12. Serial Communication (CDC)

        Instruction is based on a two ASCII bytes. Each instruction has two parts 1 byte address and one byte command. The LS byte is command and MS byte is address.

1. Components Address

The table below shows the assigned address in the system.

2. USB Top commands

The Table below shows the possible commands for controller and USB module.                                                

USB status command returns One byte status but only three Least Significant bits contains the information about the module as shown in table below.

3. JPEG encoder commands

The Table below shows the possible commands for JPEG Encoder.

JPEG Encoder module only returns one byte if status with only two least significant bit containing information. These decimal value(3-0) of two least significant bits tells the quality of encoding.

4. HDMIs

The Table below shows the possible commands for HDMIs.

HDMI module returns 265 Bytes:

5. Source selector

The Table below shows the possible commands for image selector.

Source selector returns Two bytes

6. RED, GREEN, BLUE commands

These are the common commands for all three colors.

7. VGA daughter board commands(in progress)

The Table below shows the possible commands for VGA daughter board.

8. Debug Module

The Table below shows the possible commands for VGA daughter board.

The output of Debug Module is 14 bytes:

5. Test setup

6. References and reading material