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P16X64A ASSEMBLY MANUAL
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P16X64A

'P2'

ASSEMBLY LANGUAGE

MANUAL

UNOFFICIAL DRAFT

DOCUMENT UNDER CONSTRUCTION

web document link

CONTENTS

COG REGISTERS

TIMING

P16X64A INSTRUCTION SET

INSTRUCTION FORMAT (GENERAL)

OpCode Field

ZCI (and L) Fields

CCCC Field

DDDDDDDDD Field

SSSSSSSSS Field

Part 2 - List of Instructions

COG REGISTERS

ADDR

NAME

READ

WRITE

000-1F7

RAM

RAM

1F8

PTRA

PTRA

RAM+PTRA

1F9

PTRB

PTRB

RAM+PTRB

1FA

INA

INA

RAM

1FB

INB

INB

RAM

1FC

OUTA

RAM

RAM+OUTA

1FD

OUTB

RAM

RAM+OUTB

1FE

DIRA

RAM

RAM+DIRA

1FF

DIRB

RAM

RAM+DIRB

Note: Instructions writing OUTx and DIRx also write to the shadow RAM. Therefore the shadow RAM retains the last values written to the OUTx and DIRx registers, which can then be read back (by reading the shadow RAM).

 This is useful in  read-modify-write instructions such as: ANDN DIRx,#$003 which turns off the DIRx bits [1:0].

TIMING

|<----5ns period------->|                       |                       |                       |                       |                       |

------------____________------------____________------------____________------------____________------------____________------------____________-
|                       |                       |                       |                       |                       |                       |
|-------.               |              rdRAM Ic |-------.               |              rdRAM Id |-------.               |              rdRAM Ie |
|       |               |                       |       |               |                       |       |               |                       |
|---+   +----> rdRAM Db |------------> latch Db |---+   +----> rdRAM Dc |------------> latch Dc |---+   +----> rdRAM Dd |------------> latch Dd |
|---+   +----> rdRAM Sb |------------> latch Sb |---+   +----> rdRAM Sc |------------> latch Sc |---+   +----> rdRAM Sd |------------> latch Sd |
|---+   +----> latch Ib |------------> latch Ib |---+   +----> latch Ic |------------> latch Ic |---+   +----> latch Id |------------> latch Id |
|   |                   |                       |   |                   |                       |   |                   |                       |
|   +------------------ALU-----------> wrRAM Ra |   +------------------ALU-----------> wrRAM Rb |   +------------------ALU-----------> wrRAM Rc |
|                       |                       |                       |                       |                       |                       |
|                       |       <wait a>        |                       |       <wait b>        |                       |       <wait c>        |

P16X64A INSTRUCTION SET


Notes:

Unless stated otherwise if the WZ effect is specified, the Z flag is set (1) if the resulting Value equals zero.


INSTRUCTION FORMAT (GENERAL)

31

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26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

i

i

i

i

i

i

i

Z

L

C

L

I

L

C

C

C

C

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

All instructions utilise a 32-bit instruction:

iiiiiii                        Instruction OpCode

Z                        If set (1) by WZ (with zero), then the Z (zero flag) will be updated by this instruction

C                        If set (1) by WC (with carry), then the C (cary flag) will be updated by this instruction

I                        If set (1) by #S, then the SSSSSSSSS will be used as an immediate value instead of register address

L                        If set (1) by #D, then the DDDDDDDDD will be used as an immediate value instead of register address

Note: “L”, when available, repurposes Z, C or I bit

n/nn/nnn                        Word/Byte/Nibble select (Repurposes lower opcode bit and Z C bits)

CCCC                        Conditional execution code

DDDDDDDDD        Destination address, or immediate value when L=1

SSSSSSSSSS        Source address, or immediate value when I=1


OpCode Field

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27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

i

i

i

i

i

i

i

These field bits[31:25] represent the 7-bit instruction opcode.

Note: Some extended opcode instructions also utilise a mix of the Z, C, I and SSSSSSSSS bits.

ZCI (and L) Fields

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Z

L

C

L

I

L

These field bits[24:22] represent the Z, C and I 1-bit fields for WZ (Zero flag), WC (Carry flag) and Immediate (#) S field modifier.

Some instructions my alternately utilise any of these bits as an Immediate (#) D field modifier, designated by “L”.

Those instructions capable of changing the “Zero Flag” are designated with a “Z” in bit[24].

Those instructions capable of changing the “Carry Flag” are designated with a “C” in bit[23].

Those instructions capable of utilising a 9-bit “Immediate Source Field” in bits[8:0] are designated with an “I” in bit[22].

Those instructions capable of utilising a 9-bit “Immediate Destination Field” in bits[17:9] are designated with an “L” in one of bit[24], bit[23] or bit[22].

Note: Some extended opcode instructions repurpose a mix of the Z, C and I bits, making those bits unavailable for those instructions.

CCCC Field

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

These field bits[21:18] represent the instructions’ 4-bit conditional execution bits. This 4-bit code, together with the current value of the Z (zero flag) and C (carry flag), determines whether this instruction will execute or be transformed into an effective “NOP” (no-operation) instruction.

CONDITION

INSTRUCTION EXECUTES

CCCC

SYNONYMS

IF_ALWAYS

always

1111

IF_NEVER

never

0000

IF_E

if equal (Z = 1)

1010

IF_Z

IF_NE

if not equal (Z = 0)

0101

IF_NZ

IF_A

if above (!C & !Z = 1)

0001

IF_NC_AND_NZ –and– IF_NZ_AND_NC

IF_B

if below (C = 1)

1100

IF_C

IF_AE

if above or equal (C = 0)

0011

IF_NC

IF_BE

if below or equal (C | Z = 1)

1110

IF_C_OR_Z –and– IF_Z_OR_C

IF_C

if C set

1100

IF_B

IF_NC

if C clear

0011

IF_AE

IF_Z

if Z set

1010

IF_E

IF_NZ

if Z clear

0101

IF_NE

IF_C_EQ_Z

if C equal to Z

1001

IF_Z_EQ_C

IF_C_NE_Z

if C not equal to Z

0110

IF_Z_NE_C

IF_C_AND_Z

if C set and Z set

1000

IF_Z_AND_C

IF_C_AND_NZ

if C set and Z clear

0100

IF_NZ_AND_C

IF_NC_AND_Z

if C clear and Z set

0010

IF_Z_AND_NC

IF_NC_AND_NZ

if C clear and Z clear

0001

IF_A –and– IF_NZ_AND_NC

IF_C_OR_Z

if C set or Z set

1110

IF_BE –and– IF_Z_OR_C

IF_C_OR_NZ

if C set or Z clear

1101

IF_NZ_OR_C

IF_NC_OR_Z

if C clear or Z set

1011

IF_Z_OR_NC

IF_NC_OR_NZ

if C clear or Z clear

0111

IF_NZ_OR_NC

IF_Z_EQ_C

if Z equal to C

1001

IF_C_EQ_Z

IF_Z_NE_C

if Z not equal to C

0110

IF_C_NE_Z

IF_Z_AND_C

if Z set and C set

1000

IF_C_AND_Z

IF_Z_AND_NC

if Z set and C clear

0010

IF_NC_AND_Z

IF_NZ_AND_C

if Z clear and C set

0100

IF_C_AND_NZ

IF_NZ_AND_NC

if Z clear and C clear

0001

IF_A –and– IF_NC_AND_NZ

IF_Z_OR_C

if Z set or C set

1110

IF_BE –and– IF_C_OR_Z

IF_Z_OR_NC

if Z set or C clear

1011

IF_NC_OR_Z

IF_NZ_OR_C

if Z clear or C set

1101

IF_C_OR_NZ

IF_NZ_OR_NC

if Z clear or C clear

0111

IF_NC_OR_NZ

DDDDDDDDD Field

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

D

D

D

D

D

D

D

D

D

These field bits[17:9] represent the 9-bit register address to be utilised as the destination value.

Some instructions permit the use of the “D” bits[17:9] to be utilised as an immediate (#) 9-bit value. Those instructions will utilise an “L” bit modifier in one of the bit[24:22] positions (by repurposing the Z, C or I bit).

SSSSSSSSS Field

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

S

S

S

S

S

S

S

S

S

These field bits[8:0] represent the 9-bit register address to be utilised as the source value.

Most instructions permit the use of the “S” bits[8:0] to be utilised as an immediate (#) 9-bit value. Those instructions will utilise the “I” bit modifier in bit[22].

Note: Some extended instructions repurpose the “S” bits[8:0] to extend the opcode space.

Part 2 - List of Instructions