unkown register. always read 0x0. Write some addresses higer then 0x800.0000
value = 0 or 1; or block? count + 1 (each 4096byte). max 0xffff. dma? scatter-gather DMA?
NOTE: Я смотрю в sdhci используется ADMA, где по определённому адресу список sg блоков.
looks like fifo in and out
if ADMA_Enable then value=0x10, else value=0x0
value= physical dma address. not suooprted on au6601?
value = some value (bitfield) | 0x40
command
used only together with 0x23
value = some value with endian conversation.
command parametr
regs 0x30 - 0x40, some kind of buffer. Depending on flag, should be read 0x30 only, or complete 0x30-0x3f range.
value = some value with endian conversation.
led mode. know values: 0x3; (0x4 | 1); (0x8 | 1).
looks like BIT0 should be always set.
if PwrDownCtrl=1 then value = 0x10, else value = 0x0
LED related, always togled BIT0. Other bits unknown. 0x61 and 0x63 are always set before 0x51
value = same as 0x61
value =
ms code
Size of FIFO to read (max 0x200?) is it working for write too?
value =
used always with 0x7A, same bit set and remuved at same time on both registers. Only BIT0 and BIT3 are tugled. Toggle state of CMD and VDD pins
value (bitfield) =
PLL stettings. BIT0 - enable PLL; BIT1 - ExtX2Mode, 6621 realted; BIT4-BIT7 - mult; BIT8-BIT15 - div;
value (bitfield) =
BIT4-BIT5 - Signal Control; BIT6 - Enable Interrupt delay; BIT7 - ???
value (bitfield)
part of 0x74. used values 0x1 and 0x8
value (bitfield) = 0x0 or 0x80
on read, tested bit are 0x1(sd card is present) and 0x8 (?).
pnp code
used in statement: if (reg_read(0x77) == 0), then disable ASPM. And probably set PM_enable=0
value (bitfield) = val | 0x80.
after write (val | 0x80), read this register and wait untill val ( 0x1 or 0x8) was unset by HW.
DMA TX? Abbort command?
used always together with 0x70, only BIT0 or BIT3 togled.
value (bifield) =
const value = 68
NOTE: uExtPadDrive0
const value = 68
NOTE: uExtPadDrive1
const value = 68
NOTE: uExtPadDrive2 not supported on 6601
value = wrtie 0x0 or 0x1
after 0x0 ,read and test 0x08
after 0x1, read and test 0x21
silicon revision? if read 0x21, then it is 6621; if not, then it is 6601??
CMD control register. 0x20 send command. Other bits used to set return size: R1, R2...
value =
knwo values 0x20 and 0x0. used bewore 0x86 and pll
value =
0x20 - bus width 4
0x00 - bus width 1
enable FIFO. Configure direction?0x1 - enable FIFO for read.
value (bitfield) = 0x0 or 0x80
tested: if (reg_read(0x84) & 0x800F)
if ((reg_read(0x84) & 0x800F) == 0x800F)
BIT15 - CMD
BIT3 - DAT3; 0 - DAT3 is 0; 1 - DAT3 is 1;
BIT2 - DAT2
BIT1 - DAT1
BIT0 - DAT0
value = 0x0 or 0x1... possible to set 0x7c.
always used with 0x72, pll settings.
value (bitfield) = val | 0xc0; val & 0x3f; val & 0xf0
IRQ status 0x40 - card removed; 0x80 - card inserted; 0x20 - data in FIFO start; 0x2 data in FIFO, end.
value: 0x0 or 0x7F01FB
NOTE: watchdog?
0xA1 - uchar (read write)
write value = 0x1 or 0x3
read and test : if (reg_read(0xa1) == 0x3)
0xA2 - uchar (write only)
value = val + 16
NOTE: size?
0xA3 - uchar (write only)
value (bitfield) = depends on val for 0xA2
0xB0 - ulong (read write)
value =
0xB4 - ulong