VLSI Communication Systems

Executive MS class meets January 18-19, February 15-16, March 8-9, April 12-13, May 10-11 in Room CMS 1.164, Commons Building at PRC

Direct link to this page : bit.ly/vlsicom

Link to Piazza: piazza.com/utexas/spring2012/ee382v16940

This course aims to study solutions in digital VLSI to problems arising in communication system design.

Sample applications include:

- Experimenting with different modulation schemes, and comparing their performance in the presence of noise and interference,
- Examining the trade-offs between different filter architectures with respect to numerical properties,
- Adaptive filtering to overcome the effects of multi-path spread in wireless communications, and
- Developing digital algorithms for timing and symbol recovery.

The course is targeted towards communication products rather than processors. Examples of companies that make such products are Qualcomm, TI, Broadcom, Lucent, and Cisco; many processor companies also have large communications products divisions.

This course is intended for ECE graduate students. It is self-contained, with review material on both VLSI and communication theory.

The contents of this page will likely change over time - I may change lecture topics and homework/lab problems.

- Adnan Aziz
- Email: (Please put VLSI_COMM in the subject line)
- URL: http://www.ece.utexas.edu/~adnan
- Office Hours: TuTh 2pm-3pm ACES 6.120

- Test 1: Start of Unit 4 (2 hour duration)
- Test 2: End of Unit 5 (2 hour duration)
- Here is a sample Midterm-1. Here is its solution.
- Here is a sample Midterm-2. Here is its solution.

- Introduction
- Communication Theory: (slides; my written notes) An additive function that's not linear.

- Here's a derivation of the bit-error-probability for BPSK. Another article clarifying what is.
- Carrier recovery and symbol timing recovery for QPSK.
- A very accessible set of tutorials on communication system design; the OFDM unit is especially good.
- A fairly technical survey of antennas by Balanis. Dipoles for dummies, Parts 1, 2, 3. Wikipedia surveys on antennas and dipoles.
- An account of Marconi's first transatlantic transmission, the embedded video is especially nice
- 802.11a overview, IEEE standard.
- More material on OFDM: notes from Brian Evans' class, and an article on timing recovery for OFDM.

- Hardware: Analog/RF CMOS, Digital CMOS
- Fast convolution using the FFT: we'll largely draw on Cormen, Leiserson, and Rivest "Introduction to Algorithms" Chapter 32; here are some figures.

- Here is an article describing a hardware implementation of the FFT. (HW3 requires you to answer some questions related to this implementation.)
- A talk describing the state-of-the-art in software FFT, and the homepage of the public domain software project.
- History of the FFT, dating back to Gauss; another nice perspective, with lessons learned

- Doing trig with CORDIC (The article sidesteps the issue of representing angles as sums of ; CORDIC works only because , so each successive iteration yields an angle that's less than half of what it was before.)

- Here is an article on a state-of-the-art implementation of CORDIC; the authors manage to remove the need for a scaling factor, speed up the computation, and extend the range of input angles handled.
- Brian Evans tells me that a sine wave can be generated with single CORDIC operation by using the difference equation . The output will be a sine wave with frequency when the input is an impulse.

- The equation has feedback, so there are stability issues, but you can create one wavelength, and repeat the samples. The equation yields a sine wave because the underlying system has two poles on the unit circle, at .

- If you have a hardware multiplier, you can implement trignometric functions more efficiently using power series expansions - check out this article that compares different techniques.
- Weste and Harris talk about efficient implementations of CORDIC in their CMOS design text.

- Digital Filtering in hardware: we'll be using Parhi's book - his notes are online, and in some respects are a little easier to read. Here are some of the figures we'll use for illustration.

- Introduction, Iteration bound (Ch 1, 2)
- Pipelining & Parallel Processing (Ch 3)
- Retiming (Ch 4 - we'll go in less detail; a simpler description of algorithms for retiming)
- Unfolding, Folding (Ch 5, 6)
- Recursive and Adaptive Filters (Ch 10)

- Here is a quick-and-dirty introduction to stability theory for IIR filters.
- Here are some figures illustrating the effects of incomplete pole zero cancellation; the source files are iir_finite_df1.m, iir_infinite.m, quant_and_saturate.m, and run_iir_sim.m.
- Here is an old but clear paper on implementing adaptive equalizers for disk drive read channels.
- Here are some notes on nonlinear equalization

- Numerical strength reduction (Ch 15)
- Scaling and Roundoff Noise (Ch 11)

- A toolbox for computing wordlengths for filters by Kyungtae Han and Brian Evans.
- Here is a classic paper on the impact of round-off noise on parallel, cascade, and lattice filter structures, all implementing the same transfer function.
- Another old, but very well written paper, which includes numerical results and comparison with the analytic model
- Here's the paper this chapter is largely based on. Some associated controversy: "dubious model", "reponse"

- Error correcting codes: my notes are mostly from “Error Correcting Codes” by Lin and Costello.

- Notes on data compression
- LDPCs: the best source is Robert Gallager's thesis, particularly pages 39-43. Howland and Blanksby have a nice article (JSSC March 2002) on implementing LDPC decoding in hardware
- Here is a more accessible article from CommsDesign magazine.
- There's been interest recently in randomized constructions for LDPCs - Dan Spielman has some nice work on this topic.

- Switching: a short overview of hardware issues in switch design
- Recap: a quick walk-through of what we covered in the class
- Guest Lectures

- Andrew Hocker's MS report on EtherLux: presentation slides, MS writeup
- Programmable DSPs Mike Warner's overview of DSP architectures

- Sriram Sundarajan's comments on the DSP processor versus custom debate

- Adaptive Filtering for Noise Cancellation Slides from Jay Fletcher's (ECD MS 2006) talk
- FPGAs for Signal Processing and Communication Systems Dr Raghu Rao (Xilinx) slides

- Wireless Communications: From Systems to Silicon Dr Raghu Rao (Xilinx) on the design and implementation of a complex communication protocol

- Vaidehee P. Gokhale's MS report Telemedicine via Smartphones : slides, MS Report
- Hans L. Yeager's (hansl209 at aol dot com) MS Report Mobile PowerBench: slides, MS Report
- Rafael Castro’s MS Report High Speed ADC Interface slides

- Kamran Saleem
- Email: (Please put VLSI_COMM in the subject line)
- Phone: 512-537-5913 , Skype: k.saleem

Homework and Labs

HWs are due at 11:59pm on Sunday two weeks after they are assigned. Labs are due at 11:59pm on the Sunday of the following unit.

Submission Guidelines

You can turn in a Softcopy or a Hardcopy as you like:

- Softcopy: You can create a Google Doc for your response to the HWs and LABs.

- Title should be [Yourname_VLSI_COMM_HW_#] or [Yourname_VLSI_COMM_LAB_#]

- Submission through Google Docs is a three step process:

- Make sure that the Doc is under the GoogleDoc Collection that you will be creating in HW0
- Change permissions of TA to be "Is owner" and your own permissions to be "Can view" (For PDFs, "Can edit" for the TA is fine)
- Put a link to the Doc from your class homepage that you will be creating in HW0

All of these should be done by 11:59pm on due date or your submission will be deemed late

- Hardcopy: must be turned in by 5pm on due date. You can hand over to the TA in his office hour or drop into his room ENS 122

Homework |

HW0 Getting Started |

HW1 VLSI Principles and Comm Theory |

HW2 Iteration Bound, Pipelining & Parallel Proc |

HW3 Retiming, Folding & Unfolding |

HW4 IIR and Numerical Strength Reduction |

Lab |

LAB 1 Communication System Modeling |

LAB 2 Filters - Finite Word length Effects |

LAB 3 LMS Based Adaptive Equalizer |

LAB 4 Timing Recovery Lab4.ppt Supplementary readings |

Solutions : Please find all solutions on Blackboard (courses.utexas.edu) under VLSI_COMMUNICATION / Course Documents

Please check the FAQ page regularly.

- Please see my requests for regrades policy.
- You are encouraged to interact with your peers when solving labs and homeworks. However, solutions should be written up separately, and you should note the people that you discussed the material with. Cheating will be dealt with in accordance with university policy - the gory details are described here.
- The University of Texas at Austin provides upon request appropriate academic adjustments for qualiﬁed students with disabilities. For more information, contact the Ofﬁce of the Dean of Students at 471-6259, 471-4241 TDD.
- All departmental, college and university regulations concerning drops will be followed.