Digital Logic Systems

ETE 315

Course Description:

        Introduction to sequential logic circuits, latches and flip-flops and their applications, state diagram, state table, state machines (Mealy and Moore) design, state machine converter, state machine with and without control inputs, state reduction, analysis and design of clocked sequential circuits, analysis of timing diagrams, complex sequential logic circuit design and serial data code conversion, state machine design with algorithmic state machines.

LAB 1        3

Introduction:        3

Materials:        3

Laboratory:        3

Design procedure:        3

Conclusion        5

LAB 2        6

Pre-lab:        6

Materials:        7

Laboratory:        8

LAB 3        9

Objective:        9

Materials:        9

Experiment:        9

State Table        9

JA = C KA = C’        10

JB = A’+C KB = C        10

JC = B KC = AB        10

State Diagram        10

Timing Diagram        10

Reference        10

Procedure:        11

Conclusion:        11

LAB 4        11

Objective:        12

Materials:        12

Experiment:        12

Laboratory:        13

Characteristic Equations        13

Wiring diagram        14

Conclusion:        14

LAB 5        15

Objective:        15

Equipment and Materials:        15

Introduction:        15

Part 1 Serial-IN-Parallel-OUT (SIPO) Shift Register        15

Procedure:        16

Part 2 Parallel-IN-Parallel-OUT (PIPO) Shift Register:        16

Procedure:        17

Conclusion:        17

LAB 6        18

Objectives:        18

Laboratory:        18

Procedure:        18

Block Diagram:        20

LAB 7        21

Objective:        21

Materials:        21

Prelab:        21

Laboratory:        21


LAB 1

Introduction:

        To design combinational logic circuits using MSI components. In this laboratory experiment the students will implement Boolean function using a multiplexer and decoders.

Materials:        

2 to 4 lines decoders

        4x1 multiplexer

        Logic gates

        Switches

        LEDs

Laboratory:        

Generate the following Boolean function using:

F (a,b,c) = ∑ ( 0,2,6,7 )

  1. 2 to 4 lines decoders
  2. A 4x1 multiplexer

Design procedure:

Follow these steps to design both logic circuits:

Conclusion

        Given the boolean function F (a,b,c) = ∑ ( 0,2,6,7 ), we derived truth table to show the minterms, from there we designed a circuit that fuffilled the boolean function using decoders and multiplexers. For the decoder we ran into the issue of forgeting that the outputs are inverted. We had to run all of the outputs of the decoder to an inverter back to the OR gates due to that we only had one LED. As for the multiplexer we had two designs to either use a single 4 to 1 or dual 4 to1 multiplexer as a 8 to 1, we ended up using single multiplexer.



LAB 2

Introduction:

        To analyze the sequential circuit below through characteristic equations, state table, building the circuit.

Pre-lab:

  1. Writing the characteristic equations

A+ = B

B+ = (X⊕A)B +(X⊕A)’B’ = XAB’ + X’A’B’+XA’B+X’AB

Y = (X⊕A)⊕B

  1. constructing a state table

                

X

A

B

A+

B+

Y

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  1. Draw a state diagram for the circuit.

Debounce Circuit

Materials:        

Laboratory:        

  1. Build your circuit

  1. Use a switch for the input and leds for the outputs
  2. Verify the operation of the circuit by comparing the operation of our circuit with the state table
  3. Troubleshoot your circuit if there are any problems

Conclusion

        We created a addition debounce circuit for our clock pulse to remove some of the noise that a push button clock would create so by using a NAND debounce circuit, it will make sure the clock pulse is clear and will not alter the flip flop differently than it should be. Using three inputs and two JK flip flop the next state can be determined. With the state table being completed the characteristic equation for the outputs A and B were found.

LAB 3

Objective:        

To design a 3-bit counter using JK- Flip Flops.

Materials:        

Breadboard and Wires

                JK- Flip Flops

                7-Segment decoder/driver

                7-Segment display

                Logic Gates

                Switches

                Resistors

Experiment:        

Design a 3-bit counter which has the following count sequence;

                0 -> 2 -> 3 -> 5 -> 7 -> 4 -> 0

State Table

A

B

C

A+

B+

C+

JA

KA

JB

KB

JC

KC

0

0

0

0

1

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0

X

1

X

0

X

0

0

1

x

x

x

X

X

X

X

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1

JA = C        KA = C’

JB = A’+C        KB = C

JC = B        KC = AB

State Diagram

Timing Diagram

Rising Edge

Clock

A

0

0

1

1

1

1

0

B

0

1

1

0

1

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0

C

0

1

1

1

1

0

0

Binary

0

2

3

5

7

4

0

Reference

http://www.slideshare.net/eboodani/chapter-5-counter

Procedure:

Conclusion:

This lab asked for a sequence of numbers to be shown on a 7 segment display. To do the sequence three J-K flip flops were needed. With a truth table, the next state equations for each of the three inputs can be created. From there an excitation table can be created for the JK flip flops that will be used. Using the characteristic equation for a JK flip flop, the data for the flip flops can be determined. Now that the table is filled out, a K-map will provide the next state equations for the JK flip flop. Once the system is built, the display should then follow the sequence of 0, 2, 3, 5, 7, 4.

LAB 4

Objective:        

To give students some experience in designing a simple state machine with JK flip flops.

Materials:        

Breadboard and Wires

                JK- Flip Flops

                LEDs

                Logic Gates

                Switches

                Resistors

Debounce circuit

Experiment:

A sequential circuit has three flip flops, A, B, C; one input, x; and one output y.

The state diagram is shown below.

The circuit is to be designed by treating the unused states as don’t care conditions. The final circuit must be analyzed for self-correction

Design your circuit using the following;

  1. D flip flops
  2. JK flip flops

Laboratory:

Build your circuit using JK flip flops, a toggle switch for input x, and LEDs for state conditions and output y.

 

X

A

B

C

A+

B+

C+

DA

DB

DC

JA

KA

JB

KB

JC

KC

Y

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Characteristic Equations

D Flip-flops

JK Flip-Flop

Y = XA’

DA = XA’B’

DB = A+X’C’+XBC

DC = X’C+XA+X’A’B’

Y = XA’

JA = XB’

KA = 1

JB = A+X’C’

KB = X’C + XC’ = X⊕C

JC = XA+X’A’B

KC = X

Wiring diagramete 315 lab 4 jk flipflop.png

Conclusion:

This lab asked to design a sequential circuit using JK flip flops and D flip flops from a state diagram. The diagram shows that there are 5 states in total which means that 3 JK and D flip flops are needed. Since states 5-7 are not in the state diagram they will be labeled as don’t cares in the truth table. To fill the truth table for states 0-4, the logic of the diagram was followed to see which would be the next state. With the next state table filled out the excitation table for the D and JK flip flop were created so that it can create the logic needed. K maps were then constructed to derive the characteristic equations to know what the connections should be for the flip flops. The detailed schematic shown is how the connections were made to make the circuit follow the state diagram.


LAB 5

Objective:        

To design , construct, and simulate the Serial-IN-Parallel-OUT (SIPO) and Parallel-IN-Parallel-OUT (PIPO) Shift Registers

Equipment and Materials:        

Breadboard and Wires

                Dual D Flip Flops

                Resistors

Waveform Generator

Power Supply

Introduction:

Shift Registers are made of a group of flip-flops that are connected in a chain so that the output of one of the flip-flops becomes the input of the next flip-flop. Shift Registers are a synchronous type of sequential circuit where a common clock is connected to all of the flip-flops. There are two ways of loading and two ways of shifting (serial and parallel) data that makes four different shift registers: SISO, SIPO, PISO, and PIPO. In this experiment we will construct, test, and simulate the SIPO and PIPO shift registers.

Part 1 Serial-IN-Parallel-OUT (SIPO) Shift Register

In the serial-IN-Parallel-OUT type of shift register, data bits are loaded serially and shifted in parallel format. Again, we will use D flip flops to design such a sequential circuit. Data is loaded bit-by-bit at the input port and all input data will appear at the output data at the same time. In SIPO, the output of each D flip flop reflects one bit of the input data. All clock inputs are connected to a single external clock pulse generator and therefore, the SISP circuit is a synchronous  sequential circuit. The 54/74164 is an 8-bit serial-in-parallel-out shift register chip.

Procedure:

  1. Set up a SIPO as shown in figure 2 and test your circuit with the data input of 1011, you can do this by observing the state of the LED at the output and verify that the output data is the same as the input data
  2. Change the clock pulse to slow down or speed up the data shift process

Questions:

  1. After how many clock pulses will the the 4-bit input data shift to the output port? Why?

It will take 4 clock pulses so that each bit is loaded. Because it does only shifts 1 bit at a time.

  1. What would happen if you connected the output of figure 1 to the input of figure 2?

Part 2 Parallel-IN-Parallel-OUT (PIPO) Shift Register:

The fourth type of shift register is PIPO, where the input data will shift from the input port to the output port at each clock pulse. To design this type of shift register, we simply arrange four D-Flip flops in a parallel format with a common clock and common Pre/Clr input. The 74174 is a 6 bit PIPO shift register. The 54/74198 is an 8-bit TTL MSI shift register with both parallel input and parallel output capabilities. It can also be used for bidirectional shift register, that is, it has capability of shifting an 8 bit data either to the left or to the right

Procedure:

  1. Arrange four D flip flops in a parallel format as shown in figure 4 and connect all wires accordingly
  2. Set the input data as 1011 and show that the input data will shift to the output port after the first clock pulse

Questions:

  1. What are the advantages of PIPO over the other types?

It only takes one clock cycle to send all the bits since they are independently connected.

  1. What are the disadvantages of PIPO over the other types?

There would be 4 connections required for the inputs while serial only need 1. This can become costly if you need multiple connections.

Conclusion:

This lab asked


LAB 6

Objectives:

To design a serial data circuit to detect a certain sequence of binary input.

Laboratory:

Design a serial data circuit that can detect the code '1001'. The circuit has a

single input 'X' and one output 'Y'. The output is to remain zero unless the

correct sequence is received. The circuit should detect every occurrence of the

given code.

Procedure:

A

B

X

A+

B+

Z

JA

KA

JB

KB

0

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JA= BX’

KA= X + B

JB=  X + A

KB= X’ + A     Z = ABX

Block Diagram:


LAB 7

Objective:

To design a simple traffic light controller.

Materials:

Prelab:

Design a traffic light controller using state machines

approach

which follows the following repeated time sequence:

NS

Green

EW

red

5s

NS

Yellow

EW

red

5s

NS

Red

EW

green

5s

NS

Red

EW

yellow

5s

Assume each clock tick is 5 -seconds. Use a decoder to decode outputs,.

Laboratory:

A

B

A+

B+

Da

Db

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DA= A’B+A’B

DB= B’