Parallax Propeller 2 Assembly Instruction Set

Here you  find the instruction set for the new P2 (2015) chip  Please feel free to edit this document and if something requires more explanation  or examples then just link that to another section of the document.  The emphasis is mainly on the instruction set and memory map while Chip's document provides the overview and many other details. Please refer to his document for more information about the Propeller 2 chip itself.

<click here for published version>

CONTENTS

LINKS

LABELS

EXPRESSIONS

ADDRESSING

P2 MEMORY MAP

EXEC MAP

COG REGISTERS

LUT

HUB

HUB ROM

P2 INTERNAL STACK

Conditional execution codes table

INSTRUCTION BIT-FIELD SYMBOLS

P2 INSTRUCTIONS LIST

SHIFTS ROTATES

ARITHMETIC

LOGICAL

INSTRUCTION MODIFIERS

COG NIBBLE/BYTE/WORD Operations

BRANCHING

CALL REGISTER

CALL LONG

LUT MEMORY

Example: Create stacks in LUT memory.

HUB MEMORY

SMART PINS

COG and HUB CONTROL

CORDIC

EVENTS, WAITS and INTERRUPTS

NOTES

SETTING EDGE EVENTS

ALIASES

POINTER ADDRESSING MODES

Examples:

HUB MEMORY READING AND WRITING

STREAMER

ALTDS

ALTDS Examples

copy 16 cog regs from .src to .dest

PUSHZC ??? - Old P2_hot instruction ???

RDFAST

P2 INTERNAL STACK

MAILBOXES AND DEBUG INTERRUPT VECTORS

Migrating From Propeller 1

Instruction Changes

Removed Instructions/Registers/Effects

Experimenting with different document layouts

LINKS

Link to Chip's P2 document

Link to PBJ's opcode testing   (pubdocs version)

Mindrobot's P2 memory-map architecture spreadsheet

Discussion about LUT to HUB flow is here 

LABELS

  • Labels are either globally-scoped or locally-scoped.
  • A globally-scoped label must begin with an underscore or letter (a-z, A-Z). All other characters must be an underscore, letter (a-z, A-Z) or number (0-9).
  • A locally-scoped label must begin with a period, followed by an underscore or letter (a-z, A-Z). All other characters must be an underscore, letter (a-z, A-Z) or number (0-9).
  • Each local scope begins immediately after each global label and ends immediately before the next global label.
  • All labels must be unique within the scope they belong to.

Label values are determined as follows:

  • Labels defined in an ORGH section resolve to a hub address or offset (in bytes), regardless of whether the label is referenced in an ORGH or ORG section.
  • Labels defined in an ORG section resolve to a cog address or offset (in longs), regardless of whether the label is referenced in an ORGH or ORG section.
  • When the effective hub address or offset is needed for a label that is defined in an ORG section, the label may be preceded by a "@" to force resolution to a hub address or offset.
  • Though it is possible to apply the "@" to labels defined in ORGH sections, it has no effect.

EXPRESSIONS

  • Expressions can contain numbers, labels, and nested expressions. The simplest expression is either a single number or label.
  • An expression that begins with # or ## is known as an "immediate" value.
  • For branching instructions, immediate values can be either "absolute" or "relative", depending on context.
  • For non-branching instructions, immediate values are always "absolute".
  • "Absolute immediate" interpretation can be forced by using "#\" or "##\".
  • There is no operator for forcing a "relative immediate" interpretation.
  • # indicates a 9-bit (short-form) or 20-bit (long-form) immediate value:
  • For short-form branch instructions, this is a 9-bit relative immediate.
  • For long-form branch instructions that change execution mode (cog <-> hub), this is a 20-bit absolute immediate.
  • For long-form branch instructions that do not change execution mode, this is a 20-bit relative immediate.
  • For all other instructions, this is a 9-bit absolute immediate.
  • In circumstances where an absolute immediate must be forced, the expression is prefaced with "#\".
  • ## indicates a 32-bit immediate value
  • An implicit AUGx will precede the instruction containing the expression.
  • The lower 9 bits will be encoded in the instruction and the upper 23 bits will be encoded in the AUGx.
  • For short-form branch instructions, this is a 20-bit relative immediate. The upper 12 bits are ignored.
  • For non-branch instructions, this is a 32-bit absolute immediate.
  • This is meaningless for long-form branche instructions. PNUT throws an error.
  • For BYTE/WORD/LONG, the expression is encoded as raw data. If the expression begins with # or ##, PNUT throws an error.
  • For all other expressions that do not begin with # or ##, the expression is encoded as a register address and must be between $000 and $1FF.

ADDRESSING

  • All cog register accesses are direct via instructions (MOV rega,regb).
  • All lut access is via RDLUT/WRLUT (cog registers <--> lut registers) or SETQ2+RDLONG (hub --> lut).
  • All hub accesses are via RDxxxx/WRxxxx/RFxxxx/WFxxxx, only.
  • "@", "#hublabel", "#\hublabel" refers to hub RAM, only.
  • "#@hublabel" is the same as "#hublabel".
  • "@", "#\", and "#@" cannot be used to point at anything in the cog or lut. They always denote hub memory.

All symbols defined under ORGH are hub addresses. Any reference to one of them returns a hub address.

All symbols defined under ORG are both cog and hub addresses, with a direct reference returning a cog address. Using @ before one of those symbols returns the hub address, instead.

P2 MEMORY MAP

<mindrobots cheat sheet>

Reading memory from $0000 to $03FF with RDxxxx will read from hub memory whereas a jump/call to these locations will execute from cog or lut.

EXEC MAP

ADDR

NAME

DESCRIPTION

$00_0000..$00_01EF

COG EXEC

Code executes from cog register space (self-modifying code permitted)

$00_0200..$00_03FF

LUT EXEC

Code executes from lut register space

$00_0400..$0F_FFFF

HUB EXEC

Code executes from hub space (hub uses byte addressing)

Code is not required to be long aligned

Uses instruction streamer

COG REGISTERS 

(9-bit addressable)

01F0: 0000.0000 0000.0000 0000.0000 0000.0000 0000.0000 0000.0000 0000.0980 0000.0000

01F8: 0000.131C 0000.0010 0000.0000 4000.0000 0000.0000 4000.0000 FFFF.FFFE FC00.0000

ADDR

READ

WRITE

NAME/USE

DESCRIPTION

000-1EF

RAM

RAM

user

general-purpose 32-bit registers (and cog exec code space)

1F0

RAM

RAM

IJMP3

interrupt call address for INT3

1F1

RAM

RAM

IRET3

interrupt return address for INT3

1F2

RAM

RAM

IJMP2

interrupt call address for INT2

1F3

RAM

RAM

IRET2

interrupt return address for INT2

1F4

RAM

RAM

IJMP1

interrupt call address for INT1

1F5

RAM

RAM

IRET1

interrupt return address for INT1

1F6

RAM

RAM

ADRA

receives CALLD-immediate return or LOC address

1F7

RAM

RAM

ADRB

receives CALLD-immediate return or LOC address

1F8

PTRA

PTRA

PTRA

dedicated register for hub access pointer with auto inc/dec, cog ram is not accessible

1F9

PTRB

PTRB

PTRB

dedicated register for hub access pointer with auto inc/dec, cog ram is not accessible

1FA

RAM

DIRA (+RAM)

DIRA

output enables for P0..P31

1FB

RAM

DIRB (+RAM)

DIRB

output enables for P32..P63

1FC

RAM

OUTA (+RAM)

OUTA

output states for P0..P31

1FD

RAM

OUTB (+RAM)

OUTB

output states for P32..P63

1FE

INA

RAM

INA

input states for P0..P31 (also debug shadow int call address)

1FF

INB

RAM

INB

input states for P32..P63 (also debug shadow int ret address)

LUT

ADDR

R/W

NAME

DESCRIPTION

200-3FF

RAM

user/cog-exec

HUB

Updated 151010

ADDR

R/W

NAME

DESCRIPTION

$00_0000..$07_FFFF

RAM

user/hub-exec

(hubexec does not function for hub $00000..$00FFF as it is mapped to COG & LUT)

$0F_FF80..$0F_FFBF

mailboxes

16 special longs that create r/w events

$0F_FFC0..$0F_FFFF

Cog 0..15 (initial) debug interrupt vectors (PNut does not download to this)

HUB ROM

ADDR

R/W

NAME

DESCRIPTION

$00_0000..$00_3FFF

n/a

ROM

boot only - not accessible

NTERNAL ST

P2 IACK

There is an eight level 22-bit Internal Stack in all COGs. This is accessible using the following instructions:

PUSH    D/#

push D/# on internal stack

POP     D     {WC,WZ}

pop  D from internal stack

CALL    D     {WC,WZ}

save return address on internal stack

CALL    #abs/@rel

save return address on internal stack

RET           {WC,WZ}

jump via internal stack


==================================================================================================

Conditional execution codes table

CODE

PASM directive

ALT

Description

Logic

1111

always

default

1100

if_c

if_b

if below

C

0011

if_nc

if_ae

if above or equal

NC

1010

if_z

if_e

if equal

Z

0101

if_nz

if_ne

if not equal

NZ

1000

if_c_and_z

C&Z

0100

if_c_and_nz

C&NZ

0010

if_nc_and_z

NC&Z

0001

if_nc_and_nz

if_a

if above

NC&NZ

1110

if_c_or_z

if_be

if below or equal

C|Z

1101

if_c_or_nz

C|NZ

1011

if_nc_or_z

NC|Z

0111

if_nc_or_nz

NC|NZ

1001

if_c_eq_z

C=Z

0110

if_c_ne_z

C<>Z

0000

never

forces NOP

INSTRUCTION BIT-FIELD SYMBOLS

Field

Description

S

Source address

D

Destination address

I

Immediate source

L

Immediate destination

R

Relative address

C

Effects Carry status

Z

Effects Zero status

Fixed instruction field

CCCC

Conditional execution code - default is "always"


P2 INSTRUCTIONS LIST

SHIFTS ROTATES

ROR                D ,         S/#        {wc,wz}        Rotate Right        

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2

1

0

C

C

C

C

0

0

0

0

0

0

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Rotate D right by S linking from bit 0 to bit 31. If wc is specified the C will be set if the lsb of the result = 1 ?

ROL                D ,         S/#        {wc,wz}        Rotate Left

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2

1

0

C

C

C

C

0

0

0

0

0

0

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Rotate D left by S linking from bit 31 to bit 0. If wc is specified the C will be set if the msb of the result = 1

SHR                D ,         S/#        {wc,wz}        Shift Right        

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2

1

0

C

C

C

C

0

0

0

0

0

1

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Shift D right by S with zero written to bit 31. If wc is specified the C will be set if the lsb of the result = 1

SHL                D ,         S/#        {wc,wz}        Shift Left        

31

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2

1

0

C

C

C

C

0

0

0

0

0

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Shift D left by S with zero written to bit 0. If wc is specified the C will be set if the msb of the result = 1

RCR                D ,         S/#        {wc,wz}        Rotate Carry Right        

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9

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4

3

2

1

0

C

C

C

C

0

0

0

0

1

0

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

x

RCL                D ,         S/#        {wc,wz}        Rotate Carry Left        

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9

8

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6

5

4

3

2

1

0

C

C

C

C

0

0

0

0

1

0

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

x

SAR                D ,         S/#        {wc,wz}        Shift Arithmetic Right        

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14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

0

0

0

1

1

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Shift Arithmetic right and preserve sign

SAL                D ,         S/#        {wc,wz}        Shift Arithmetic Left        

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12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

0

0

0

1

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Shift Arithmetic left and preserves lsb

ARITHMETIC

ADD                D ,         S/#        {wc,wz}        Add S to D        

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9

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6

5

4

3

2

1

0

C

C

C

C

0

0

0

1

0

0

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Add S to D unsigned. If the wc is specified then the carry flag is set if there is an overflow

ADDX                D ,         S/#        {wc,wz}        Add S and carry to D        

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10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

0

0

1

0

0

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Add S with carry to D unsigned. If the wc is specified then the carry flag is set if there is an overflow

ADDS                D ,         S/#        {wc,wz}        Add signed S to D        

31

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29

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10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

0

0

1

0

1

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Add S to D signed. If the wc is specified then the carry flag is set if there is an overflow

ADDSX        D ,         S/#        {wc,wz}        Add signed S with carry  to D        

31

30

29

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12

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9

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6

5

4

3

2

1

0

C

C

C

C

0

0

0

1

0

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Add S with carry to D signed. If the wc is specified then the carry flag is set if there is an overflow

SUB                D ,         S/#        {wc,wz}        Subtract S from D        

31

30

29

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27

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25

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15

14

13

12

11

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9

8

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6

5

4

3

2

1

0

C

C

C

C

0

0

0

1

1

0

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Subtract S from D unsigned. If the wc is specified then the carry flag is set if there is an overflow

SUBX                D ,         S/#        {wc,wz}        Subtract S with carry from D        

31

30

29

28

27

26

25

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23

22

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18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

0

0

1

1

0

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Subtract S with carry from D unsigned. If the wc is specified then the carry flag is set if there is an overflow

SUBS                D ,         S/#        {wc,wz}        Subtract signed S from D        

31

30

29

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25

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17

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14

13

12

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10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

0

0

1

1

1

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Subtract S from D signed. If the wc is specified then the carry flag is set if there is an overflow

SUBSX        D ,         S/#        {wc,wz}        Subtract signed S with carry from D        

31

30

29

28

27

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25

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18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

0

0

1

1

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Subtract S with carry from D signed. If the wc is specified then the carry flag is set if there is an overflow

CMP                D ,         S/#        {wc,wz}        Compare S to D        

31

30

29

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13

12

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10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

0

1

0

0

0

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Comapre S to D unsigned. If the wc is specified then the carry flag is set if there is an overflow

CMPX                D ,         S/#        {wc,wz}        Compare S with carry to D        

31

30

29

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27

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17

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15

14

13

12

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10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

0

1

0

0

0

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Compare S with carry to D unsigned. If the wc is specified then the carry flag is set if there is an overflow

CMPSX        D ,         S/#        {wc,wz}        Compare signed S with carry to D        

31

30

29

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17

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15

14

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12

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9

8

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6

5

4

3

2

1

0

C

C

C

C

0

0

1

0

0

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Compare S with carry to D signed. If the wc is specified then the carry flag is set if there is an overflow

CMPR                D ,         S/#        {wc,wz}        Compare Reverse (D to S)

31

30

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14

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12

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10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

0

1

0

1

0

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Compare D to S (reversed) unsigned. If the wc is specified then the carry flag is set if there is an overflow

CMPM                D ,         S/#        {wc,wz}        Compare (MSB) S to D  

31

30

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3

2

1

0

C

C

C

C

0

0

1

0

1

0

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Compare S to D unsigned. If the wc is specified then the carry flag is set with the MSB of the (unwritten) result

SUBR                D ,         S/#        {wc,wz}        Subtract Reverse (D from S)  

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5

4

3

2

1

0

C

C

C

C

0

0

1

0

1

1

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Subtract D from S unsigned with result in D. If the wc is specified then the carry flag is set if these is an overflow

CMPSUB        D ,         S/#        {wc,wz}        Compare S to D and Subtract if S<=D

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3

2

1

0

C

C

C

C

0

0

1

0

1

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Compare S to D unsigned and subtract S from D if it is lesser or equal. If the wc is specified then the carry flag is set if these is an overflow?

MIN                D ,         S/#        {wc,wz}        Minimum limit

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5

4

3

2

1

0

C

C

C

C

0

0

1

1

0

0

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Limit value of D to a minimum of S

MAX                D ,         S/#        {wc,wz}        Maximum limit

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5

4

3

2

1

0

C

C

C

C

0

0

1

1

0

0

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Limit value of D to a maximum of S

MINS                D ,         S/#        {wc,wz}        Minimum Signed limit

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6

5

4

3

2

1

0

C

C

C

C

0

0

1

1

0

1

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Limit signed value of D to a minimum of S

MAXS                D ,         S/#        {wc,wz}        Maximum Signed limit

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5

4

3

2

1

0

C

C

C

C

0

0

1

1

0

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Limit signed value of D to a maximum of S

SUMC                D ,         S/#        {wc,wz}        Sum Carry signed

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6

5

4

3

2

1

0

C

C

C

C

0

0

1

1

1

0

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Sum signed value of D with the signed value of S which is negated if C=1

SUMNC        D ,         S/#        {wc,wz}        Sum Not Carry signed

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6

5

4

3

2

1

0

C

C

C

C

0

0

1

1

1

0

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Sum signed value of D with the signed value of S which is negated if C=0

SUMZ                D ,         S/#        {wc,wz}        Sum Zero signed

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8

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6

5

4

3

2

1

0

C

C

C

C

0

0

1

1

1

1

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Sum signed value of D with the signed value of S which is negated if Z=1

SUMNZ        D ,         S/#        {wc,wz}        Sum Not Zero signed

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9

8

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6

5

4

3

2

1

0

C

C

C

C

0

0

1

1

1

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Sum signed value of D with the signed value of S which is negated if Z=0

MUL                D ,         S/#        {wc,wz}        Multiply 16x16

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8

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6

5

4

3

2

1

0

C

C

C

C

0

1

1

1

1

1

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Multiply 16-bit S with 16-bit D with a 32-bit result in D

MULS                D ,         S/#        {wc,wz}        Multiply Signed 16x16

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9

8

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6

5

4

3

2

1

0

C

C

C

C

0

1

1

1

1

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Multiply signed 16-bit S with 16-bit D with a 32-bit signed result in D

ABS                D ,         S/#        {wc,wz}        Absolute value

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6

5

4

3

2

1

0

C

C

C

C

0

1

1

0

0

1

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Absolute value of S into D, that is negate the value of S if it is negative to make it positive.

NEG                D ,         S/#        {wc,wz}        Negate value

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9

8

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6

5

4

3

2

1

0

C

C

C

C

0

1

1

0

0

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Negate value of S into D.

NEGC                D ,         S/#        {wc,wz}        Negate value if Carry set

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13

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11

10

9

8

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6

5

4

3

2

1

0

C

C

C

C

0

1

1

0

1

0

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Get value S into D and negate if C=1.

NEGNC        D ,         S/#        {wc,wz}        Negate value if Not Carry

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14

13

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11

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9

8

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6

5

4

3

2

1

0

C

C

C

C

0

1

1

0

1

0

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Get value S into D and negate if C=0.

NEGZ                D ,         S/#        {wc,wz}        Negate value if Zero set

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17

16

15

14

13

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11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

1

1

0

1

1

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Get value S into D and negate if Z=1.

NEGNZ        D ,         S/#        {wc,wz}        Negate value if Not Zero

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14

13

12

11

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9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

1

1

0

1

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Get value S into D and negate if Z=0.

LOGICAL

ISOB                D ,         S/#        {wc,wz}        Isolate Bit

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13

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9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

1

0

0

0

0

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Isolate bit D[S/#] into C.

NOTB                D ,         S/#        {wc,wz}        Not Bit

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8

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6

5

4

3

2

1

0

C

C

C

C

0

1

0

0

0

0

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Invert bit D[S/#] and set C to bit before it was inverted

CLRB                D ,         S/#        {wc,wz}        Clear bit

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17

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9

8

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6

5

4

3

2

1

0

C

C

C

C

0

1

0

0

0

1

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Clear bit D[S/#] and set C to bit before it was clear

SETB                D ,         S/#        {wc,wz}        Set bit

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9

8

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6

5

4

3

2

1

0

C

C

C

C

0

1

0

0

0

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Clear bit D[S/#] and set C to bit before it was set

SETBC        D ,         S/#        {wc,wz}        Set bit to C

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11

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9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

1

0

0

1

0

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Set bit D[S/#] to C and set C to bit before it was modified

SETBNC        D ,         S/#        {wc,wz}        Set bit to Not C

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14

13

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11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

1

0

0

1

0

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Set bit D[S/#] to Not C and set C to bit before it was modified

SETBZ        D ,         S/#        {wc,wz}        Set bit to Z

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14

13

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11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

1

0

0

1

1

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Set bit D[S/#] to Z and set C to bit before it was modified

SETBNZ        D ,         S/#        {wc,wz}        Set bit to Not Z

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18

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16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

1

0

0

1

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Set bit D[S/#] to Not Z and set C to bit before it was modified

ANDN                D ,         S/#        {wc,wz}        AND Not

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15

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13

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11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

1

0

1

0

0

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

AND the Not of S to D

AND                D ,         S/#        {wc,wz}        AND

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13

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11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

1

0

1

0

0

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

AND S to D

OR                D ,         S/#        {wc,wz}        OR

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11

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9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

1

0

1

0

1

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

OR S to D

XOR                D ,         S/#        {wc,wz}        XOR

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13

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11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

1

0

1

0

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

XOR S to D

MUXC                D ,         S/#        {wc,wz}        MUX C

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14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

1

0

1

1

0

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Set the bits in D according to C using the mask in S

MUXNC        D ,         S/#        {wc,wz}        MUX Not C

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13

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11

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9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

1

0

1

1

0

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Set the bits in D according to Not C using the mask in S

MUXZ                D ,         S/#        {wc,wz}        MUX Z

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22

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17

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15

14

13

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11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

0

1

0

1

1

1

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Set the bits in D according to Z using the mask in S

MUXNZ        D ,         S/#        {wc,wz}        MUX Not Z

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C

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C

Z

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D

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D

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Set the bits in D according to Not Z using the mask in S

NOT                D ,         S/#        {wc,wz}        NOT

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Z

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D

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D

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D

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D

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S

Invert the bits in S to D

TESTN        D ,         S/#        {wc,wz}        Test Not bits

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Z

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S

Test the bits in D using the inverted mask in S and set Z and C accordingly

TEST                D ,         S/#        {wc,wz}        Test bits

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Z

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D

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D

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S

Test the bits in D using the mask in S and set Z and C accordingly

ANYB                D ,         S/#        {wc,wz}        Any Bit

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C

Z

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D

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D

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D

D

D

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OR S and D without modification and set C=any bit set, Z=result = 0

TESTB        D ,         S/#        {wc,wz}        Test Bit

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C

Z

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D

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D

D

D

D

D

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S

Test bit D[S/#] and set C/Z to state ???

INSTRUCTION MODIFIERS

ALTI        D ,         S/#                        Alter D/S in the next instruction

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D

D

D

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D

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D

D

D

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S

Uses a D register for D/S field substitutions in the next instruction, while S/# modifies the D register's D and S fields and controls D/S substitution.

This is the old ALTDS without the wc,wz options.

ALTR        D ,         S/#                        Alter R in the next instruction

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C

C

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1

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D

D

D

D

D

D

D

D

D

S

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S

S

Use the sum of D and S/# for the result register in the next instruction

ALTD        D ,         S/#                        Alter D in the next instruction

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C

C

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C

0

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I

D

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D

D

D

D

D

D

D

S

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S

S

Use the sum of D and S/# for the D register in the next instruction

ALTS        D ,         S/#                        Alter S in the next instruction

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C

C

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1

I

D

D

D

D

D

D

D

D

D

S

S

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S

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S

S

S

Use the sum of D and S/# for the S register in the next instruction

RGBSQZ        D ,         S/#                        RGB Squeeze

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C

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I

D

D

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D

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D

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D

S

S

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S

Squeeze RGB

RGBEXP        D ,         S/#                        RGB Expand

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C

C

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D

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D

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D

S

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S

Expand RGB

ADDPIX        D ,         S/#                        ADD Pixels

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C

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I

D

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S

Add pixlels

MULPIX        D ,         S/#                        Multiply Pixels

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I

D

D

D

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D

S

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S

Multiply pixlels

BLNPIX        D ,         S/#                        Blank Pixels

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C

C

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C

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I

D

D

D

D

D

D

D

D

D

S

S

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S

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S

S

S

Blank pixlels?

MIXPIX        D ,         S/#                        Mix Pixels

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C

C

C

C

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D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Mix pixlels

REV                D ,         S/#                        Reverse bits

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C

C

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C

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I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

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S

S

S

Reverse the bits in S and write to D (changed from P1)

SETI                D ,         S/#                        Set Instruction field

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I

D

D

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S

Set Instruction field (b27..b19)? of Destination with Source

SETD                D ,         S/#                        Set Destination field

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D

D

D

D

D

D

D

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D

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S

Set destination field of D with S

SETS                D ,         S/#                        Set Source field

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I

D

D

D

D

D

D

D

D

D

S

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S

S

Set source field of D with S

REP                D/# ,         S/#                        Repeat instruction block

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L

I

D

D

D

D

D

D

D

D

D

S

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S

S

Repeat following dest instructions by source count  where 0 = infinite

AUGS                #S(23)                                Augment source of next instruction

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C

C

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C

1

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0

n

n

n

n

n

n

n

n

n

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n

n

n

n

n

n

n

n

n

n

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n

n

Augment the next instruction by extending its source field to a full 32-bits ( 9+23 ) <test>

Augment the next instruction's S or D field with additional 23-bits taken from b31..b9 of the assembler supplied parameter (b8..b0 are disregarded in PNut)

AUGD                #D(23)                                Augment destination of next instruction

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C

C

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1

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1

1

n

n

n

n

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n

Augment the next instruction by extending its destination field to a full 32-bits ( 9+23 ) <test>

SETCZ        D/#                {wc,wz}        Set C and Z flags

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C

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C

Z

L

D

D

D

D

D

D

D

D

D

0

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0

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0

Set the carry and zero flags to b1 and b0 of D. If WC is applied then C = b1 of D and Z = b0 of D

TOPONE        D ,         S/#        {wc,wz}        Top one

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C

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C

Z

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D

D

D

D

D

D

D

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D

S

S

S

S

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S

S

S

Index of most significant bit that is set to 1, C is set to (S/# = 0)

BOTONE        D ,         S/#        {wc,wz}        Bottom one

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C

C

C

C

0

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0

1

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Index of least significant bit that is set to 1, C is set to (S/# = 0)

INCMOD        D ,         S/#        {wc,wz}        Increment Modulo

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C

C

C

C

0

1

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1

0

0

C

Z

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D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

D = (D==S ? 0 : D+1) Increment to S/# then wrap to zero. (inclusive)

DECMOD        D ,         S/#        {wc,wz}        Decrement Modulo

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C

C

C

C

0

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C

Z

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D

D

D

D

D

D

D

D

D

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S

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S

S

S

D = (D==S ? 0 : D-1) Decrement to zero then wrap to S/#.

DECOD        D ,         S/#        {wc,wz}        Decode alias MASK

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0

C

C

C

C

0

1

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1

0

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1

C

Z

I

D

D

D

D

D

D

D

D

D

 S

 S

 S

 S

S

S

S

S

S

Decode index in S[4..0] into a mask in D. All other bits are set to 0.

MOV                D ,         S/#        {wc,wz}        Move

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C

C

C

C

0

1

1

0

0

0

0

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Move from cog source to cog destination

NOT                D ,         S/#        {wc,wz}        Not

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C

C

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C

0

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1

0

0

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1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Bitwise negation, Z = (result = 0), C = result[31]

LOC                reg ,         #abs/@rel                Locate

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C

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1

W

W

R

n

n

n

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n

n

Locate the 20-bit address in hub and load into a pointer register. W: ?   R: ?    ADRA / ADRB

COG NIBBLE/BYTE/WORD Operations

SETNIB        D ,         S/#,        #n                Set Nibble

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C

C

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C

1

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n

n

n

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Set the nth nibble in the cog register D to S[3..0]

GETNIB        D ,         S/#,        #n                Get Nibble

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C

C

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1

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n

n

n

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Get the nth nibble in the cog register S to D[3..0] ???

ROLNIB        D ,         S/#,        #n                Rotate Left Nibble

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28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

0

1

0

n

n

n

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Rotate the cog register D left by 4 bits, then add nth nibble in S

SETBYTE        D ,         S/#,        #n                Set Byte

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

0

1

1

0

n

n

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Set the nth byte in the cog register D to S[7..0]

GETBYTE        D ,         S/#,        #n                Get Byte

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

0

1

1

1

n

n

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Get the nth byte in the cog register S to D[7..0]

ROLBYTE        D ,         S/#,        #n                Rotate Left Byte

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

0

0

0

n

n

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Rotate the cog register D left by 8 bits, then add nth byte in S

SETWORD        D ,         S/#,        #n                Set Word

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

0

0

1

0

n

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Set the nth word in the cog register D to S[15..0]

GETWORD        D ,         S/#,        #n                Get Word

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

0

0

1

1

n

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Get the nth word in the cog register S to D[15..0]

ROLWORD        D ,         S/#,        #n                Rotate Left Word

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

0

1

0

0

n

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Rotate the cog register D left by 16 bits, then add nth word in S

SETBYTS        D ,         S/#                        Set Bytes

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

0

1

0

1

0

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Set ?

MOVBYTS        D ,         S/#                        Move Bytes

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

0

1

0

1

1

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Move ?

SPLITB        D ,         S/#                        Split Bytes

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

0

1

1

0

0

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Split ?

MERGEB        D ,         S/#                        Merge Bytes

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

0

1

1

0

1

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Merge ?

SPLITW        D ,         S/#                        Split Words

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

0

1

1

1

0

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Split ?

MERGEW        D ,         S/#                        Merge Words

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

0

1

1

1

1

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Merge ?

SEUSSF        D ,         S/#                        SEUSS Forward

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

1

0

0

0

0

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Overwrite register “D (0-511)” with a pseudo random bit pattern seeded from the value in source.

After 32 forward iterations, the original bit pattern is returned.

SEUSSR        D ,         S/#                        SEUSS Reverse

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

1

0

0

0

1

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Set ?

BRANCHING

Relative jumps are 9-bit signed so instructions such as DJNZ may jump forward as well as backward.

DJZ                D ,         S/@                        Decrement and Jump if Zero

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

1

1

0

0

0

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Decrement dest and if zero jump to source (9-bit signed relative)

DJNZ                D ,         S/@                        Decrement and Jump if Not Zero

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

1

1

0

0

1

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Decrement dest and if NOT zero jump to source (9-bit signed relative)

DJS                D ,         S/@                        Decrement and Jump if Signed

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

1

1

0

1

0

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Decrement dest and if signed positive jump to source (9-bit signed relative)

DJNS                D ,         S/@                        Decrement and Jump if Not Signed

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

1

1

0

1

1

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Decrement dest and if NOT signed positive jump to source (9-bit signed relative)

TJZ                D ,         S/@                        Test and Jump if Zero

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

1

1

1

0

0

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Test dest and if zero jump to source (9-bit signed relative)

TJNZ                D ,         S/@                        Test and Jump if Not Zero

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

1

1

1

0

1

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Test dest and if NOT zero jump to source (9-bit signed relative)

TJS                D ,         S/@                        Test and Jump if Signed

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

1

1

1

1

0

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Test dest and if signed positive jump to source (9-bit signed relative)

TJNS                D ,         S/@                        Test and Jump if Not Signed

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

0

1

1

1

1

1

1

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Test dest and if NOT signed positive jump to source (9-bit signed relative)

JMPREL        D/#                                Jump relative indexed

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

1

0

1

0

1

1

0

0

L

D

D

D

D

D

D

D

D

D

0

0

0

1

1

0

0

0

0

Jump relative to the instruction using the index which automatically adjusts for hub (x4) or cog memory

Example

        jmprel        index                'works in both cog and hub
        jmp        #pgm0
        jmp        #pgm1
        jmp        #pgm2
        jmp        #pgm3

CALL REGISTER

CALL                D                 {wc,wz}        Call

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

1

0

1

0

1

1

C

Z

0

D

D

D

D

D

D

D

D

D

0

0

0

1

0

1

1

0

1

Call indirectly via dest register and use the internal hardware stack (8 levels)

CALLA        D                 {wc,wz}        Call using PTRA

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

1

0

1

0

1

1

C

Z

0

D

D

D

D

D

D

D

D

D

0

0

0

1

0

1

1

1

0

Call indirectly via dest register and use PTRA for the stack pointer

CALLB        D                 {wc,wz}        Call using PTRB

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

1

0

1

0

1

1

C

Z

0

D

D

D

D

D

D

D

D

D

0

0

0

1

0

1

1

1

1

Call indirectly via dest register and use PTRB for the stack pointer

POP                D                 {wc,wz}        Pop hardware stack

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

1

0

1

0

1

1

C

Z

0

D

D

D

D

D

D

D

D

D

0

0

0

1

0

1

0

1

1

Pop the return address from the hardware stack into register (23 bits?)

PUSH                D/#                                 Push hardware stack

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

1

0

1

0

1

1

0

0

L

D

D

D

D

D

D

D

D

D

0

0

0

1

0

1

0

1

0

Push the register or immediate value onto the hardware stack

RET                D                 {wc,wz}        Return

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

1

0

1

0

1

1

C

Z

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

1

Return via the hardware stack

RETA                D                 {wc,wz}        Return using PTRA

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

1

0

1

0

1

1

C

Z

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

1

0

Return via the PTRA stack

RETB                D                 {wc,wz}        Return using PTRB

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

1

0

1

0

1

1

C

Z

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

1

1

Return via the PTRB stack

CALLD        D ,         S/@        {wc,wz}        Call and link D

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

0

1

0

1

0

1

C

Z

I

D

D

D

D

D

D

D

D

D

S

S

S

S

S

S

S

S

S

Call dest and save return in register S ?

CALL LONG

JMP                #abs20/@rel20                Jump to 20-bit absolute or relative address

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

1

0

1

1

0

0

R

n

n

n

n

n

n

n

n

n

n

n

n

n

n

n

n

n

n

n

n

Call the 20-bit absolute or relative address and use the internal hardware stack (8 levels)

CALL                #abs20/@rel20                Call 20-bit absolute or relative address

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

C

C

C

C

1

1

0

1

1

0

1

R

n

n

n

n

n

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Call the 20-bit absolute or relative address and use the internal hardware stack (8 levels)

CALLA        #abs20/@rel20                Call subroutine at 20-bit absolute or relative address

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Call the 20-bit absolute or relative address and use PTRA for the stack pointer

CALLB        #abs20/@rel20                Call subroutine at 20-bit absolute or relative address

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Call the 20-bit absolute or relative address and use PTRB for the stack pointer

CALLD        reg,#abs20/@rel20                Call subroutine at 20-bit absolute or relative address

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Call the 20-bit absolute or relative address and store the return address in index register "ww" (PTRA,PTRB,ADRA,ADRB)

LUT MEMORY

These instructions are mainly used to construct stacks as they work in a similar way to WRLONG and RDLONG.

WRLUT        D/# ,         S/#                        Write to LUT memory

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D

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Write to LUT RAM where S is the pointer to write D to

RDLUT        D ,         S/#        {wc,wz}        Read from LUT memory        

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Read from LUT memory

Example: Create stacks in LUT memory.

Pushing data to an incrementing stack

        wrlut                mydata,stkptr                ' Save mydata

        add                stkptr,#1

Popping data from an incrementing stack

        sub                stkptr,#1

        rdlut                mydata,stkptr                ' restore mydata from top of stack

HUB MEMORY

WMLONG        D ,        S/#/PTRx                Write masked long

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Works like WRLONG but doesn't write $FF bytes, works with SETQ/SETQ2

RDBYTE        D ,        S/#/PTRx {wc,wz}        Read Byte from hub

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Read byte from hub using S for pointer

RDWORD        D ,        S/#/PTRx {wc,wz}        Read Word from hub

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Read unaligned word from hub using S for pointer

RDLONG        D ,        S/#/PTRx {wc,wz}        Read Long from hub

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Read unaligned long from hub using S for pointer

WRBYTE        D/# ,        S/#/PTRx                Write Byte to hub

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Write byte to hub using S for pointer

WRWORD        D/# ,        S/#/PTRx                Write Word to hub

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Write word to hub using S for pointer

WRLONG        D/# ,        S/#/PTRx                Write Long to hub

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Write long to hub using S for pointer

SETQ                D/#                                Set HUB repeat

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Repeat HUB memory op (RDxxxx/WRxxxx) with auto increment. D = count-1

SETQ2        D/#                                Set LUT repeat

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Repeat LUT memory op (RDxxxx/WRxxxx) with auto increment. D = count-1

RDFAST        D/# ,        S/#                        Read Fast setup

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Setup a RDFAST block with D 64-byte blocks starting from address S

WRFAST        D/# ,        S/#                        Write Fast setup

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Setup a WRFAST block with D times 64-byte blocks starting from address S before wrapping.

To make wrapping work S needs to be long aligned. If D = 0 = infinite then there is no wrapping.

FBLOCK        D/# ,        S/#                        Fast Block

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Fast Block

RFBYTE        D                {wc,wz}        Read Fast Byte

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Read fast byte

RFWORD        D                {wc,wz}        Read Fast Word

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Read fast word

RFLONG        D                {wc,wz}        Read Fast Long

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Read fast long

WFBYTE        D/#                {wc,wz}        Write Fast Byte

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Write fast byte

WFWORD        D/#                {wc,wz}        Write Fast Word

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Write fast word

WFLONG        D/#                {wc,wz}        Write Fast Long

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Write fast long

SMART PINS

COND

INSTR

ZCR

DEST

SOURCE

NAME

OPER

EFFECTS

DESCRIPTION

CCCC

1011110

0LI

DDDDDDDDD

SSSSSSSSS

SETPAE

D/#,S/#

Set Port A Edges ?

CCCC

1011110

1LI

DDDDDDDDD

SSSSSSSSS

SETPAN

D/#,S/#

Set Port A edge polarity?

CCCC

1011111

0LI

DDDDDDDDD

SSSSSSSSS

SETPBE

D/#,S/#

Set Port B Edges ?

CCCC

1011111

1LI

DDDDDDDDD

SSSSSSSSS

SETPBN

D/#,S/#

Set Port B Edges ?

CCCC

1100001

1LI

DDDDDDDDD

SSSSSSSSS

MSGOUT

D/#,S/#

CCCC

1010111

CZI

DDDDDDDDD

SSSSSSSSS

MSGIN

D,S/#

{WC,WZ}

CCCC

1100000

0LI

DDDDDDDDD

SSSSSSSSS

JP

D/#,S/@

Jump to source if dest pin is high (dest spans ports)

CCCC

1100000

1LI

DDDDDDDDD

SSSSSSSSS

JNP

D/#,S/@

Jump to source if dest pin is low (dest spans ports)

CCCC

1100101

0LI

DDDDDDDDD

SSSSSSSSS

XINIT

D/#,S/#

transfer init, reset phase

CCCC

1100101

1LI

DDDDDDDDD

SSSSSSSSS

XZERO

D/#,S/#

transfer init, reset phase

CCCC

1100110

0LI

DDDDDDDDD

SSSSSSSSS

XCONT

D/#,S/#

transfer update, wait for rollover, continue

SMART PINS - INSTRUCTIONS
--------------------------------------------------------------------------------------------------------------------------------------
WSBYTE        D/#,S/#                'write D[07:0] to pin S[5:0] data, mode dependent
WSWORD        D/#,S/#                'write D[15:0] to pin S[5:0] data, mode dependent
WSLONG        D/#,S/#                'write D[31:0] to pin S[5:0] data, mode dependent
WSMODE        D/#,S/#                'write D[31:0] to pin S[5:0] mode %MMMMM_FFFFCIOHHHLLL

RSBYTE        D,S/#                'read byte from pin S[5:0] into D, mode dependent
RSLONG        D,S/#                'read long from pin S[5:0] into D, mode dependent

A = IN from this pad, B = IN from other pad, B OUT = OUT to other pad

                                pad        pad
MMMMM        Description                DIR        OUT        Pattern                        Setup                                Update
--------------------------------------------------------------------------------------------------------------------------------------
00000        OUT (default)                DIR        OUT
00001        B OUT                        DIR        B OUT
00010        CLK                        DIR        CLK
00011 *        transitions                DIR        mode        update-period-repeat        WSBYTE=prescaler                WSLONG=transitions

00100 *        duty                        DIR        mode        update-period-repeat        WSBYTE=prescaler                WSLONG=adder ~
00101 *        nco                        DIR        mode        update-period-repeat        WSBYTE=prescaler                WSLONG=adder ~
00110 *        pwm sawtooth 16:16        DIR        mode        update-period-repeat        WSBYTE=prescaler                WSLONG=F:T, WSWORD=T ~
00111 *        pwm triangle 16:16        DIR        mode        update-period-repeat        WSBYTE=prescaler                WSLONG=F:T, WSWORD=T ~

01000 *        count highs                DIR **        OUT        period-update-repeat        WSLONG=period (0=cont)                RSLONG=count ~
01001 *        count lows                DIR **        OUT        period-update-repeat        WSLONG=period (0=cont)                RSLONG=count ~
01010 *        count all edges                DIR **        OUT        period-update-repeat        WSLONG=period (0=cont)                RSLONG=count ~
01011 *        count positive edges        DIR **        OUT        period-update-repeat        WSLONG=period (0=cont)                RSLONG=count ~

01100 *        time highs                DIR **        OUT        event-update-repeat                                        RSLONG=count ~
01101 *        time lows                DIR **        OUT        event-update-repeat                                        RSLONG=count ~
01110 *        time highs/lows                DIR **        OUT        event-update-repeat                                        RSLONG=count ~ (MSB=state)
01111 *        time positive edges        DIR **        OUT        event-update-repeat                                        RSLONG=count ~

10000 *        DAC cog channel                DIR        OUT        event-update-repeat        WSLONG=period
10001 *        DAC random per period        DIR        OUT        event-update-repeat        WSLONG=period
10010 *        DAC 16-bit dither        DIR        OUT        event-update-repeat        WSLONG=period                        WSWORD=value ~
10011 *        DAC 16-bit pwm LSB        DIR        OUT        event-update-repeat        WSLONG=period                        WSWORD=value ~

10100 *        A-high inc, B-high dec        DIR **        OUT        period-update-repeat        WSLONG=period (0=cont)                RSLONG=count ~
10101 *        A-rise inc, B-rise dec        DIR **        OUT        period-update-repeat        WSLONG=period (0=cont)                RSLONG=count ~
10110 *        A-B encoder                DIR **        OUT        period-update-repeat        WSLONG=period (0=cont)                RSLONG=count ~
10111 *        pulse, wait B                DIR        mode        period-update-repeat        WSLONG=16:16 H:L period                RSLONG=last wait for B ~

11000 *        sync tx byte, B clk        DIR        mode        transmit-wait-repeat        WSWORD=baud ***                        WSBYTE=data ~~
11001 *        sync tx long, B clk        DIR        mode        transmit-wait-repeat        WSWORD=baud ***                        WSLONG=data ~~
11010 *        sync rx byte, B clk        DIR **        OUT        wait-receive-repeat        WSWORD=baud ***                        RSBYTE=data ~
11011 *        sync rx long, B clk        DIR **        OUT        wait-receive-repeat        WSWORD=baud ***                        RSLONG=data ~

11100 *        async tx byte                DIR        mode        transmit-wait-repeat        WSWORD=baud                        WSBYTE=data ~~
11101 *        async tx long                DIR        mode        transmit-wait-repeat        WSWORD=baud                        WSLONG=data ~~
11110 *        async rx byte                DIR **        OUT        wait-receive-repeat        WSWORD=baud                        RSBYTE=data ~
11111 *        async rx long                DIR **        OUT        wait-receive-repeat        WSWORD=baud                        RSLONG=data ~

 * DIR from cogs: 0=reset, 1=start; IN to cogs: 1=done; !OUT from cogs clears done
** set %HHHLLL to %111111 (float/float) if your intent is to input
*** for tx, update data after B-rise; for rx, sample data before b-rise (delay input data by one clk)
 ~ data is buffered
~~ data is double buffered

COG and HUB CONTROL

ADDCT1        D ,        S/#                        Add and set Clock Tick 1

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D

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D

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D

S

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S

S

S

S

Adds S/# to D, and sets internal timer counter 1 to the same value

ADDCT2        D ,        S/#                        Add and set Clock Tick 2

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D

D

D

D

D

D

D

D

D

S

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S

S

Adds S/# to D, and sets internal timer counter 1 to the same value

ADDCT3        D ,        S/#                        Add and set Clock Tick 3

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1

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D

D

D

D

D

D

D

D

D

S

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S

S

Adds S/# to D, and sets internal timer counter 1 to the same value

COGINIT        D/# ,         S/#        {wc}                Cog Init        

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L

I

D

D

D

D

D

D

D

D

D

S

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S

Initialize Cog  

D[8:6]                        Reserved

D[5] = %0                Copy $1F8 longs from Hub @PTRB into cog, then JMP to $000

D[5] = %1                JMP to PTRB

D[4:0] = %1----        Target cog is lowest-numbered inactive cog

D[4:0] = %0nnnn        Target cog is indicated by %nnnn

S                        Address of first instruction to execute, copied to PTRB of the target cog

Q                        20-bit value provided by SETQ, copied to PTRA of the target cog

{WC}                        If D[4] = %1  and D is not an immediate value:

COGID        D/#                 {wc,wz}        Cog ID        

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D

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D

D

D

D

D

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D

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0

0

1

Read the Cog's ID

COGSTOP        D/#                                 Cog Stop        

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D

D

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D

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1

 

Stop the Cog

CLKSET        D/#                 {wc,wz}        Clock Set

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C