1. Instructor
  2. Text
  3. Grading
  4. Important Dates
  5. Lectures
  6. Course Supplement
  7. Homeworks
  8. Labs
  9. Teaching Assistants and Grader
    1. Discussion Sections
  10. Resources

EE316 - Fundamentals of Logic Design

Fall 2009: meets MWF noon-1:00pm in ACA 1.104; unique number 16415.


This course aims to study the design of digital hardware, specifically the problem of realizing computation with logic gates.  


Prerequisites: EE306 or CS 307, and credit/registration for EE 312 or CS 310.


We will begin by reviewing basic facts about binary arithmetic and Boolean logic. This will be followed by an in-depth study of combinational logic design, starting with implementation general logic functions with NAND-NOR gates, followed by specific design styles for muxes, decoders, and programmable logic, and then an introduction to design using the VHDL hardware description language.


Next we will study the design and implementation of sequential logic.  Specifically, we will study the basic building blocks in the form of latches and flops, and clocks.  We will then study how to design, optimize, and test general sequential circuits using state charts as well as VHDL. 


We will conclude with survey level treatment of arithmetical circuits, and system level design with VHDL.


All departmental, college and university regulations concerning drops will be  followed. The University of Texas at Austin provides upon request appropriate academic adjustments for qualified students with disabilities. For more information, contact the Office of the Dean of Students at 471-6259, 471-4241 TDD. 

The contents of this page will likely change over time - I may change lecture topics and homework/lab problems.

Instructor

Text

Fundamentals of Logic Design, 6 Edition, by Charles Roth and Larry Kinney. The latest edition of the text is required. The best price I can find is $143.95 at Amazon.com. The book includes a CDROM with software that you will need to perform the labs - it runs on Windows XP and Vista.

Known errors in the book.

Grading


The first midterm will be based on material covered up to the date of the midterm, the second midterm will cover material starting after the first midterm and up to the date of the midterm.  I may possibly cover less, and will post an explicit list of topics before exams. The final will be comprehensive, with an emphasis on topics covered after the second midterm. 

Important Dates

Test dates will not change, barring emergencies.


HW and Lab dues dates are posted on the HW and Lab sections.

Lectures

Unit Topic Dates Advanced Readings
Unit 1 Introduction, Number Systems and Conversion Week 0 (8/26-8/29)
Unit 2-3 Boolean Algebra Week 1 (8/31-9/4) Boolean Logic; Shannon's MS thesis. Knuth on Boolean Algebra.
Unit 4 Applications of Boolean Algebra Week 2 (9/7-9/11) CNF
Unit 5 Karnaugh maps Week 2 (9/7-9/11) Exact and Heuristic 2-level Minimization
Unit 7 Multi-level logic with NAND and NOR gates Week 3 (9/14-9/18) Multilevel logic: basics; common logic extraction; design with a limited gate library. Knuth on logic circuits.
Unit 8 Design and simulation of combinational logic Week 4 (9/21-9/25) Timing Models for Logic Circuits; Circuit simulation with SPICE
Unit 9 Muxes, decoders, and PLDs Week 5 (9/28-10/2) SRAMs; CAMs, ROMs & PLAs
Unit 10 Introduction to VHDL Week 6 (10/5-10/9) VHDL Library Example
Unit 11 Latches and flip-flops Week 7 (10/12-10/16) Circuit design for latches & flops
Unit 12 Registers and counters Week 8 (10/19-10/23)
Unit 13 Analyzing sequential logic Week 9 (10/26-10/30) What I learned at Google
Unit 14-15 State graphs and tables, state minimization Week 10 (11/2-11/6)
Unit 16 Sequential circuit design Week 11 (11/9-11/13) Optimizing sequential logic Poor code: 1, 2, 3
Unit 17 VHDL for sequential logic Week 12 (11/16-11/20) Video Lecture
Unit 18 Arithmetical circuits Week 13 11/23-11/27) Advanced arithmetical circuits Video Lecture
Unit 20 Digital system design with VHDL Week 14 (11/30-12/4)

Course Supplement

A 62 page course supplement is required.  It contains material on the labs, with specific instructions on using the Xilinx board that are not available elsewhere.  It will be available from Friday 8/28/2009 onwards from the Welch Copy Center.  The cost will be approximately $6.50.

Homeworks

Homeworks will be due in class on Fridays, at the start of lecture. They will be collected by the appropriate TA, and returned in class.

Put your name and instructor on each page.

If you have questions about a graded homework, the TAs will have solutions, but you cannot copy them in any way. Because of widespread sharing of solutions on the web, we will not post solutions.

  • HW1:  1.2 (4), 1.7 (10), 1.14 (10), 1.24 (10), 1.25 (8), 1.27 (6), 2.5 (6), 2.7 (6) (Week 1)  = 60  Graded by Arnab
  • HW2:  3.6 (6), 3.29 (6), 3.31 (12), 4.1 (8), 4.2 (8), 4.15 (8), 4.21 (6), 4.40 (6) (Week 2) = 60  Graded by Hooman
  • HW3:  5.7 (12), 5.13 (9), 5.32 (6), 5.26(8), 5.34 (15) (Week 3) = 60  Graded by Faisal
  • HW4:  7.2 (8), 7.21 (14), 7.22 (8), 7.24 (9), 7.26 (5), 7.38 (8), 7.42 (8) (Week 4) = 60  Graded by Chengqing
  • HW5:  8.3 (6), 8.10 (4), 8.14 (5), 8.15 (4), 9.4 (6), 9.7 (8), 9.8 (6), 9.21 (12), 9.32 (9) (Week 6) = 60  Graded by Ansab
  • HW6:  10.1 (4 ), 10.4 (6), 10.9 (10), 10.20 (21), 11.2 (5), 11.3 (4), 11.6 (4), 11.14 (6) (Week 8) = 60  Graded by Arnab
  • HW7:  12.1 (4), 12.7 (8), 12.25 (6), 12.32(6), 12.35 (9), 13.2 (2), 13.5 (6), 13.11 (10), 13.17 (9) (Week 10) = 60  Graded by Hooman
  • HW8:  14.5 (8), 14.9 (9), 14.11 (10), 14.43 (8) 15.1 (3), 15.4 (6), 15.11 (6) (Week 11) = 60  Graded by Faisal
  • HW9:  16.10 (10), 16.20 (12), 16.27 (9), 17.3 (6), 17.8 (3), 17.18 (12), 17.28 (8) (Due Monday, 11/23, Week 13) = 60 27 Graded by Chengqing
  • HW10: 18.4 (10), 18.7 (16), 18.20 (10), 18.21 (12), 18.27 (12) (Week 14) = 60 32 Graded by Ansab
  • HW11: 20.2, 20.6, 20.8 (Not to be turned in - practice for finals)

Numbers in parens denote scores for each question.

Link to HW FAQs.

Labs

Here is a link to the labs page.

Teaching Assistants and Grader

TA sections and office hours will be held in ENS 202.  This room has 40 workstations connected to Xilinx boards which will be used for some of the labs.  There is a whiteboard which TAs will use for review.

Discussion Sections

Monday Tuesday Wednesday Thursday
1000-1100 Arnab 930-1030 Faisal 1100-1200 Arnab
 1100-1200 Hooman
100-200 Hooman 1230-130 Ansab
 200-300 Chengqing 200-300  Chengqing
300-400 Ansab
 330-430 Faisal


Lab Hours

Here is a link to the Google Calendar with TA  lab hours. Sections are the busiest times; the TAs tend to be freer in the mornings.

Contact Information


Name Email
Chengqing Hu (TA)
 boren.hu+316@ google 
Ansab Ali (TA)
 ansabali.316 @ google
Arnab Dutta (TA)

arnab1984.iit+316@ google
Hooman Rahimzade (TA)
 hooman_rahimzade@ yahoo
Biwei Yin (Grader)
 biweiyin+316@ google
Faisal Iqbal (TA) mfiqbal@ google
Amber Hassan (Consulting TA)

amber@mail dot utexas            

New TAs - Boole and Claude.

TA Responsibilities


  • Conduct office hours: I expect the complete 20 hours committed each week - 12 hours in the office, 8 hours of grading/emailing/lecture
    • Your presence is required even if no students show up 
    • If you need to travel, e.g., for a job interview, it's your responsibility to find coverage
  • Be courteous to students, help with any question (but do not give away answers)
    • If someone is rude/unreasonable, ask them to contact me
  • Respond to all emails in a timely manner
  • Collect all HWs/labs in class,
    • Grade within one week (maximum, sooner preferred)
    • Handle all regrade requests. Perform HW and lab grading
  • Prepare solutions to labs, HWs, and exams
  • Assist with exam preparation, printing, grading
    • Totaling, entering scores, generating stats
  • Maintain website: specifically, FAQ for labs and homeworks
  • Prepare short tutorials on design software
  • Attend  lectures
  • Add link to personal URL under name on table - URL should have basic contact information

Resources

  • Similar classes at Berkeley, Stanford, Michigan
  • Two other classic texts: Digital Design by Mano, Digital Design: Principles and Practices, by Wakerly
  • My VLSI design class talks about how to build gates; my logic synthesis class talks about how you can design algorithms that optimize networks of gates
  • Designing a CPU with 2-i/p NORs and tristates
    • This was one of 7 problems in a three hour hardware prelim exam taken by PhD students at Berkeley.  The solution from the professor (Randy Katz) is at the end - it's a single page, illustrating the power of hiearchical thinking.
  • Class discussion group (Experimental)

  • Buy your own Xilinx Spartan 3 board from Digilent, approximately $110
    • Note: lacks the add-on clock debounce board we have on the lab boards
  • Other sections
    • Ramesh Yerraballi, TTh 500-630, ACA 1.104 (Final: Thursday, December 10, 7:00–10:00 pm)
    • Nur Touba, TTh 330-500 WEL 2.312 (Final: Wednesday, December 9, 2:00–5:00 pm)