Statement of Course Outcomes
Course Number: CS 514
Course Name: Computer Architecture
Course Coordinator: David Klappholz
Graduate or Undergraduate Equivalent: CS 488
Catalog Description: Measures of cost, performance, and speedup; instruction set design; processor design; hard-wired and microprogrammed control; memory hierarchies; pipelining; input/output systems; and additional topics as time permits. The emphasis in this course is on quantitative analysis of design alternatives. Prerequisite: CS 550 or equivalent.
Course Outcomes
Each course outcome is followed in parentheses by the Program Outcome to which it relates.
CS 514 Computer Architecture
Goals: Students who successfully complete this course will learn the basic principles of computer design through quantitative methods.
Objectives: Students who successfully complete this course will be able to:
1. State and use the basic quantitative principles of computer design and performance measurements. (Homework exercises are assigned and graded. Students are tested through exam questions)
2. State and consider the role of today’s technology and the factors affecting the cost of computer systems. (Homework exercises are assigned and graded. Students are tested through exam questions)
3. State and consider price-performance measurements of processors designed for desktop, server, and embedded systems, as well as the role of power efficiency in design of processors. (Homework exercises are assigned and graded. Students are tested through exam questions)
4. Design basic and intermediate RISC pipelines, including the instruction set, data paths, and ways of dealing with pipeline hazards. (Homework exercises are assigned and graded. Students are tested through exam questions)
5. Compare various pipeline designs and performance, while identifying the trade–off between performance and hardware complexity. (Homework exercises are assigned and graded. Students are tested through exam questions)
6. Consider use of dynamic scheduling in processor design, and use of basic methods to implement dynamic scheduling. (Homework exercises are assigned and graded. Students are tested through exam questions)
7. Consider various techniques of instruction-level parallelism, including superscalar execution, branch prediction, and speculation, in design of high-performance processors. (Homework exercises are assigned and graded. Students are tested through exam questions)
8. Consider use of static approaches to exploiting instruction-level parallelism to improve performance by relying on more sophisticated compiler technology. (Homework exercises are assigned and graded. Students are tested through exam questions)
9. State and understand memory hierarchy design, memory access time formula, performance improvement techniques, and trade-offs. (Homework exercises are assigned and graded. Students are tested through exam questions)
10. Compare the effect of memory hierarchy (main and caches) designs using benchmark data. (Homework exercises are assigned and graded. Students are tested through exam questions)
11. State and compare various memory organizations, bandwidth optimizations, and the effect on their cost-performance. (Homework exercises are assigned and graded. Students are tested through exam questions)
12. State and compare properties of multiprocessor systems shared and distributed memory architectures, and their application domain, evaluating both organizational principles and effect on performance. (Homework exercises are assigned and graded. Students are tested through exam questions)
13. State and understand the cache coherency in multiprocessors and the protocols for achieving it. (Homework exercises are assigned and graded. Students are tested through exam questions)
14. State and understand the computer organization, including CPU-memory bus, I/O buses, interfaces, and communication. (Homework exercises are assigned and graded. Students are tested through exam questions)
15. State and understand the role of disk systems in providing reliability, availability, their MTTF and MTTR. (Homework exercises are assigned and graded. Students are tested through exam questions)
16. State and compare the characteristics of magnetic disks and their organization, evaluation of throughput based on speed and organization, etc. (Homework exercises are assigned and graded. Students are tested through exam questions)
17. Use Little’s queuing theory to measure the performance of some basic I/O systems. (Homework exercises are assigned and graded. Students are tested through exam questions)
18. State the organization of a vector processor, its application domain, performance comparison with a uniprocessor, and their application domains. (Homework exercises are assigned and graded. Students are tested through exam questions)
19. (Time Permitting) Learn from additional topics in computer architecture, such as papers on IA-64, MIPS-64, PowerPC, multi-core processors, and switching. (Students are tested through exam questions)